TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 33

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

3.3.7
Block
SYSCR2<HALTM1:0>
CPU
I/O ports
TMRA,TMRB0
SIO, SBI
AD converter
WDT
LCDC, SDRAMC
Interrupt controller
RTC, MLD
(1) HALT modes
HALT Mode
Standby Controller
IDLE1 or STOP mode, depending on the contents of the SYSCR2<HALTM1:0>
register.
When the HALT instruction is executed, the operating mode switches to IDLE2,
The subsequent actions performed in each mode are as follows:
a. IDLE2: Only the CPU halts.
b. IDLE1: Only the oscillator and the RTC (Real time clock) and MLD continue to
c. STOP: All internal circuits stop operating.
The operation of each of the different HALT modes is described in Table 3.3.3.
Table 3.3.2 SFR Setting Operation during IDLE2 Mode
TMRA01
TMRA23
TMRB0
SIO0
SIO1
AD converter
WDT
SBI
Table 3.3.3 I/O Operation during HALT Modes
The internal I/O is available to select operation during IDLE2 mode by
setting the following register.
Table 3.3.2 shows the registers of setting operation during IDLE2 mode.
operate.
Internal I/O
Keep the state when the HALT instruction
was executed.
Available to select
operation block
91C820A-31
Operate
IDLE2
11
TA01RUN<I2TA01>
TA23RUN<I2TA23>
TB0RUN<I2TB0>
SC0MOD1<I2S0>
SC1MOD1<I2S1>
ADMOD1<I2AD>
WDMOD<I2WDT>
SBI0BR0<I2SBI0>
SFR
Stop
Table 3.3.6 and Table 3.3.7
Operational
available
IDLE1
10
Stop
STOP
TMP91C820A
01
2008-02-20