TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 281

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

3.16.2
Operation Description
(1) Memory access control
address area, the SDRAMC outputs SDRAM control signals (SDCS, SDRAS, SDCAS,
SDWE, SDLDQM, SDUDQM, SDCLK, SDCKE).
through
SDACR<SMUXW1:0>. The relation between multiplex width and memory size is Table
3.16.1.
The SDRAMC is enabled by setting SDACR<SMAC> to “1”.
When one of the bus masters (CPU, LCDC) generates a cycle to access the SDRAM
In the access cycle, address multiplex outputs row/column multiplex address
Note: In SDRAM access cycle, WAIT setup by the CS/WAIT controller (CS1) is
fixation.
a refresh cycle are automatically inserted in CPU cycle front and back.
SDRAM access by CPU is performed by the 1 word burst mode.
SDRAM access by LCDC is performed by 1 page burst mode.
SDRAM access cycle is shown in Figure 3.16.2 to Figure 3.16.7.
The read cycle by CPU is the 4-state fixation, and a write cycle is the 3-state
In the burst read cycle by LCDC, a mode register setup, a pre-charge cycle, and
Pin Name
SDRAM
Address
A1
BS0
BS1
A10
A11
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
disregarded. The wait setting of CS1 should be 0 waits.
−
TMP91C820A address pin name
to
Table 3.16.1 Address Multiplex
A12
Address
Column
A10
A11
A12
A13
A14
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
pin.
91C820A-279
TMP91C820A Address Output
16 Mbits
And
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A0
A9
−
multiplex
Row Address
64 Mbits
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A0
A9
width
Effective column address
128 Mbits
A17
A10
A11
A12
A13
A14
A15
A16
A18
A19
A20
A21
A22
A23
is
A0
decided
TMP91C820A
2008-02-20
by
Memory size
setting