TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 334

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

Symbol
INTCLR
DMA0V
DMA1V
DMA2V
DMA3V
DMAR
DMAB
IIMC
DMA 0
request
vector
DMA 1
request
vector
DMA 2
request
vector
DMA 3
request
vector
Interrupt
clear
control
DMA
software
request
register
DMA burst
request
register
Interrupt
input mode
control
Interrupt control (3/3)
Name
Address
(Prohibit
(Prohibit
(Prohibit
RMW)
RMW)
RMW)
8CH
80H
81H
82H
83H
88H
89H
8AH
Always
write “0”.
W
7
−
0
Always
write “0”.
W
6
−
0
91C820A-332
INT3
edge
0: Rising
1: Falling
DMA0V5
DMA1V5
DMA2V5
DMA3V5
I3EDGE
CLRV5
W
5
0
0
0
0
0
0
Clears interrupt request flag by writing to DMA start vector
INT2
edge
0: Rising
1: Falling
DMA0V4
DMA1V4
DMA2V4
DMA3V4
I2EDGE
CLRV4
W
4
0
0
0
0
0
0
INT1
edge
0: Rising
1: Falling
DMA0V3
DMA1V3
DMA2V3
DMA3V3
I1EDGE
DMAR3
DMAB3
CLRV3
DMA0 start vector
DMA1 start vector
DMA2 start vector
DMA3 start vector
R/W
R/W
W
3
0
0
0
0
0
0
0
0
1: DMA request on burst mode
R/W
R/W
R/W
R/W
1: DMA request in software
W
INT0
edge
0: Rising
1: Falling
DMA0V2
DMA1V2
DMA2V2
DMA3V2
I0EDGE
DMAR2
DMAB2
CLRV2
R/W
R/W
W
2
0
0
0
0
0
0
0
0
INT0
0: Edge
1: Level
DMA0V1
DMA1V1
DMA2V1
DMA3V1
DMAR1
DMAB1
CLRV1
I0LE
R/W
R/W
W
1
0
0
0
0
0
0
0
0
TMP91C820A
2008-02-20
1: O
DMA0V0
DMA1V0
DMA2V0
DMA3V0
NMIREE
DMAR0
DMAB0
CLRV0
tion even
on
rising
edge
R/W
R/W
pera-
W
0
0
0
0
0
0
0
0
0
NMI