TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 93

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

(2) Port C1, C4 (RXD0, 1)
(3) Port C2 (
SCLK0,
SCLK1
input
CTS0
CTS1
SCLK0,
SCLK1
output
channels. In case of use RXD0/RXD1, it is possible to logical invert by setting the
register PC<PC1, 4>.
the register PCFC2<P70F2>.
input/output for the serial channels. In case of use
invert by setting the register PC<PC2, 5>.
PC write
Output latch
,
,
Port C1 and C4 are I/O port pins and can also be used as RXD input for the serial
And input data of SIO0 can be select from RXD/PC1 pin or OPTRX0/P70 by setting
Port C2 and C4 are I/O port pins and can also be used as
PC read
S
Logical invert
RXD0,
RXD1
Function control
Ditection control
Ditection control
Output latch
PCFC write
PCCR write
(on bit basis)
PCCR write
PC write
(on bit basis)
(on bit basis)
CTS0
Reset
PC read
Reset
S
Logical
invert
, SCLK0), C5 (
Logical invert
Figure 3.5.37 Port C1 and Port C4
Figure 3.5.38 Port C2 and Port C5
B
A
Selector
Selector
Selector
S
S
S
91C820A-91
B
A
A
CTS1
B
, SCLK1)
CTS
, SCLK, it is possible to logical
PC2 (SCLK0,
PC5 (SCLK1,
PC1 (RXD0)
PC4 (RXD1)
CTS
CTS0
CTS1
input or SCLK
TMP91C820A
)
)
2008-02-20