TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 267

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

Note: Because the connection between the line of display RAM data and output bus: LD0:7 is just the
3.14.4.7 Interface Examples at SR Mode
mirror reverse, please care of connection. The data LSB of display RAM is output from LD7. In the
above figure, LD0 shoud be connected to DI7 of LCD driver, and LD1 to DI6.
For detail information, please refer to Figure 3.14.5.
Note 1: Display memory should be 16-bit bus.
Note 2: Other circuit is necessary for LCD drive power supply for LCD driver display.
TMP91C820A
Figure 3.14.17 Interface Example for Shift Register Type LCD Driver
Control signal
LD0 to LD7
D0 to D15
A0 to A23
DLEBCD
D1BSCP
D3BFR
D2BLP
DOFF
VDD
VSS
Display memory
(SDRAM/SRAM selection)
Power
supply
circuit
T6C13B
(240-row driver selection)
VDD
VSS
DIR
TEST
Di7 to Di0
DUAL
SCP
S/C
VCCL/R, V0L/R,
V1L/R, V4L/R,
V5L/R
91C820A-265
VSS
O240
O001
Open
VSS
VDD
LP
FR
COM001
COM240
SCP
DI7 to DI0
EIO1
DSPOF
EIO2
T6C13B
(240-column driver selection)
240COM × 240SEG
LCD
Power supply circuit
TMP91C820A
2008-02-20