TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 37

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

Interrupt for
<RSYSCK>
A0 to A23
D0 to D15
SYSCR0
release
0 (fc)
1 (fs)
RD
WR
Figure 3.3.8 Timing Chart for STOP Mode Halt State Cleared by Interrupt
X1
c.
Table 3.3.5 Sample Warm-up Times after Clearance of STOP Mode
STOP mode
oscillator pin status in STOP mode depends on the settings in the
SYSCR2<SELDRV, DRVE> register. Table 3.3.6, Table 3.3.7 summarizes the state
of these pins in STOP mode.
warm-up time has elapsed, in order to allow oscillation to stabilize. After STOP
mode has been cleared, either NORMAL mode or SLOW mode can be selected
using the SYSCR0<RSYSCK> register. Therefore, <RSYSCK>, <RXEN> and
<RXTEN> must be set see the sample warm-up times in Table 3.3.5.
an interrupt.
When STOP mode is selected, all internal circuits stop, including the internal
After STOP mode has been cleared system clock output starts when the
Figure 3.3.8 illustrates the timing for clearance of the STOP mode halt state by
Data
01 (2
7.1 µ s
7.8 ms
8
)
91C820A-35
STOP
mode
SYSCR2<WUPTM1:0>
Warm-up
time
500
10 (2
0.455 ms
14
)
ms
at f
OSCH
= 36 MHz, fs = 32.768 kHz
2000
11 (2
1.820 ms
Data
16
TMP91C820A
)
ms
2008-02-20