TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 55

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

Symbol Name Address
Symbol Name Address
INTCLR
IIMC
INT0 level enable
NMI
0
1
0
1
rising edge enable
Interrupt
input mode
control
Interrupt
clear
control
edge detect INT
H level INT
INT request generation at falling edge
INT request generation at rising/falling edge
(2) External interrupt control
(3) Interrupt request flag clear register
(4) Micro DMA start vector registers
vector, as given in Table 3.4.1 to the register INTCLR.
operation after execution of the DI instruction.
source with a micro DMA start vector that matches the vector set in this register is
assigned as the micro DMA start source. When the micro DMA transfer counter value
reaches zero, the micro DMA transfer end interrupt corresponding to the channel is
sent to the interrupt controller, the micro DMA start vector register is cleared, and the
micro DMA start source for the channel is cleared. Therefore, to continue micro DMA
processing, set the micro DMA start vector register again during the processing of the
micro DMA transfer end interrupt.
channel; the channel with the lowest number has a higher priority.
channels, the interrupt generated in the channel with the lower number is executed
until micro DMA transfer is complete. If the micro DMA start vector for this channel is
not set again, the next micro DMA is started for the channel with the higher number.
(Micro DMA chaining.)
(Prohibit
(Prohibit
RMW)
RMW)
8CH
88H
The interrupt request flag is cleared by writing the appropriate micro DMA start
For example, to clear the interrupt flag INT0, perform the following register
INTCLR ← 0AH: Clears interrupt request flag INT0.
This register assigns micro DMA processing to an interrupt source. The interrupt
If the same vector is set in the micro DMA start vector registers of more than one
Accordingly, if the same vector is set in the micro DMA start vector registers of two
Always
write “0”.
7
7
−
0
Always
write “0”.
6
6
−
0
91C820A-53
INT3EDGE
0: Rising
1: Falling
I3EDGE
CLRV5
5
5
0
0
INT2EDGE
0: Rising
1: Falling
I2EDGE
CLRV4
4
0
4
0
W
INT1EDGE
0: Rising
1: Falling
I1EDGE
CLRV3
Interrupt vector
3
3
0
0
W
INT0EDGE
0: Rising
1: Falling
I0EDGE
CLRV2
2
0
2
0
0: INT0
1: INT0
CLRV1
edge
mode
level
mode
I0LE
1
1
0
0
TMP91C820A
2008-02-20
1: Operates
NMIREE
even on
rising/
falling
edge of
CLRV0
NMI
0
0
0
0