TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 279

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

3.16 SDRAM Controller (SDRAMC)
(1) Support SDRAM
(2) Automatic initialize function
(3) Access mode
(4) Access cycle
(5) Refresh cycle auto generate
Notes:
TMP91C820A includes SDRAM controller which supports data access by CPU/LCDC.
The features are as follows.
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16- or 64- or 128-Mbit SDRAM (× 16 bits × 2/4 BANKs), not support DDR
Display data has to set from the head of each page.
Program is not operated on SDRAM.
Following condition is set by setting Chip select controller CS1.
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Burst length
Addressing mode
CAS latency (Clock)
Write mode
All BANK pre-charge command generate
Mode register set generate
8 times auto refresh
CPU access (Read/write)
LCDC burst access (Read only)
Auto refresh is generated during another area access.
Refresh interval is programmable.
Self refresh is supported
WAIT setting: 0 WAIT setting only
Bus width: 8/16 bit only
Memory area: Optional
Read cycle: 4 states (222 ns at 36 MHz)
Write cycle: 3 states (167 ns at 36 MHz)
Access data width: 8 bits/16 bits
Burst length: 1 word only
Read cycle: 1 state (55 ns at 36 MHz)
Overhead: 4 states (222 ns at 36 MHz)
Access data width: 16 bits only
Burst length: Full page only
91C820A-277
CPU Access
Single write
Sequential
1 word
2
LCDC Access
Sequential
Full page
2
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TMP91C820A
2008-02-20