TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 263

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

Note: The speed of BaseSCP mode is equal to 2clk mode in the 8 or 16 GRAY mode.
SCPW
Base
3.14.4.6 Timing Charts of Interpreting Memory Codes
2 clk
4 clk
8 clk
LD7 to LD0
LD7 to LD0
LD7 to LD0
SDRAM burst modes, and the size of SDRAM is 16M/64M/128Mbits. The access
signals for the LCD panel are shown in Figure 3.14.12. To catch low speed LCD drivers,
3 types of SCP rates (f
to LD0) will be issued from the built-in FIFO at the rising edge of D1BSCP when the
FIFO is no empty. The work of the FIFO is illustrated in Figure 3.14.13, where the
buffer size 80 bytes. The FIFO latches BaseLD7 to LD0 signal at the falling edge of
BaseSCP which is shown in Figure 3.14.14 and 3.14.15 for SRAM and SDRAM modes
respectively. The FIFO is always reset to the empty state by the rising edge of D2BLP.
In BaseSCP mode (e.g., for SCPW1, 0 = 00), D1BCP is equal to BaseSCP, LD7 to LD0
equal to BaseLD7 to LD0 and no FIFO used. Generally, the data input rate of FIFO
should be greater than the output one.
SFR properly.
and t
relation means that the last LD7 to LD0 data must be generated before the rising edge
of D2BLP.
SDRAM burst mode, the following table can be obtained, which tells user that 8 clock
mode is impossible and SCPW = base/2/4 clock modes can be used.
D1BSCP
D1BSCP
D1BSCP
frequency
D1BSCP
Figure 3.14.12 Timing Diagram for the LCD Panel Access Signals
TMP91C820A supports different memory accessing. They are SRAM with waits,
To make FIFO work correctly, the following condition have to be satisfied by setting
Here, N is the segment number, and tcw is D1BSCP clock cycle, t
For example, in case of f
(MHz)
18
f
9
4.5
2.25
SYS
LPH
(N/8 + 1) × tcw + 24 × 1/f
is High width of D2BLP signal. Referring Figure 3.14.16, we can know this
OUT − 1
OUT − 1
tcw (ns)
111.2
222.4
444.8
OUT
55.6
OUT − 1
SYS
OUT + 1 OUT + 2 OUT + 3 OUT + 4
/2, f
91C820A-261
C
(N/8+1) × tcw + T_busdly
SYS
= 36 MHz, f
OUT
+ T_busfmax (ns)
/4, and f
C
< t
18681.6
36696
LP
5166.1
9674.4
− t
SYS
S
OUT + 1
LPH
= 32 kHz, 4 gray, 240 com, 640 seg, and
OUT
/8) can be selected. The output data (LD7
t
SCP 8 clocks
LP
SCP 2 clocks
SCP 4 clocks
− t
31250
31250
31250
31250
LPH
(ns) Judgment
LP
is D2BLP cycle,
TMP91C820A
ERROR
OK
OK
OK
2008-02-20