TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 192

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

INTSBI interrupt
request
INTSBI interrupt
request
SDA line
SCL line
SDA line
SCL line
<PIN>
<PIN>
Figure 3.10.15 Example of when <BC2:0> = 000, <ACK> = 1 in Receiver Mode
When the <TRX> = 0 (Receiver mode)
Figure 3.10.16 Termination of Data Transfer in Master Receiver Mode
Read SBI0DBR
D7
0 → <ACK>
read SBI0DBR
<ACK> to 1 and read the received data from SBI0DBR to release the SCL line
(Data which is read immediately after a slave address is sent is undefined). After
the data is read, <PIN> becomes 1.
level from SDA pin with acknowledge timing.
TMP91C820A pulls down the SCL pin to the low level. The TMP91C820A outputs
a clock pulse for 1 word of data transfer and the acknowledge signal each time
that received data is read from the SBI0DBR.
0 before reading data which is 1 word before the last data to be received. The last
data word does not generate a clock pulse as the acknowledge signal. After the
data has been transmitted and an interrupt request has been generated, set
<BC2:0> to 001 and read the data. The TMP91C820A generates a clock pulse for a
1-bit data transfer. Since the master device is a receiver, the SDA line on the bus
remains high. The transmitter interprets the high signal as an ACK signal. The
receiver indicates to the transmitter that data transfer is complete.
generated, the TMP91C820A generates a stop condition (See Section 3.10.6 (4))
and terminates data transfer.
D7
1
1
When the next transmitted data is other than 8 bits, set <BC2:0> again. Set
Serial clock pulse for transferring new 1 data is defined SCL and outputs “L”
An INTSBI interrupt request then occurs and the <PIN> becomes 0. Then the
In order to terminate the transmission of data to a transmitter, clear <ACK> to
After the one data bit has been received and an interrupt request been
D6
D6
2
2
D5
D5
3
3
91C820A-190
D4
D4
4
4
D3
D3
5
5
D2
D2
6
6
D1
D1
7
7
D0
D0
8
8
Output from master
Output from slave
ACK
Output of master
Output of slave
9
1
001 → <BC2:0>
read SBI0DBR
TMP91C820A
Acknowledge signal
sent to a transmitter
Acknowledge signal
to a transmitter
New D7
2008-02-20