TMP91xy20AFG Toshiba, TMP91xy20AFG Datasheet - Page 290

• Manufacturer Part Number: TMP91xy20AFG
• Manufacturer: Toshiba

Specifications of TMP91xy20AFG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M
• Rom Combinations: 8
• Ram Combinations: 8
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 1
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 77
• Power Supply Voltage(v): 3.0 to 3.6

A1 to A12
SDUDQM
SDLDQM
SDRAS
SDCAS
SDCKE
SDCLK
SDCS
SDWE
A11
(3) SDRAM Initialize
the time of the power-supply injection to SDRAM. The cycle is shown in Figure 3.16.10.
halted. Before executing the initialization sequence, appropriate port settings must be
made to enable the SDRAM control signals and address signals (A1 to A12).
All bank
precharge
After reset release, TMP91C820A can generate the cycle of the following required at
1. Precharge of all banks
2. The initial configuration to a mode registers
3. The refresh cycle of 8 cycles
The above mentioned cycle is generated by setting 1 to SDACR<SDINI>.
While this cycle is executing, the CPU operation (instruction fetch, execution) is
620
220
Mode
register
set
(1 word)
Auto
refresh
Figure 3.16.10 Initialize Cycle
91C820A-288
Auto
refresh
8 times auto-refresh cycle
Auto
refresh
Auto
refresh
Auto
refresh
TMP91C820A
2008-02-20