peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 106

• Manufacturer Part Number: peb20560
• Description: Dsp Oriented Pbx Controller Doc
• Manufacturer: Infineon Technologies Corporation

Semiconductor Group
2.5
Frame Synchronization Clock with Delay, which indicates the 32’nd time-slot start,
related to the standard FSC. Used for synchronization of layer-1 devices connected to
the second half of an extended IOM-2 interface with 64 time-slots; (i.e. two OCTAT-P
connected to one 4 Mbit/s IOM-2 port).
The FSCD depends on the work mode of the PEDIU (PCM DSP Interface Unit):
PEDIU Work Mode 0/1:
PEDIU Work Mode 2/3:
PEDIU Work Mode 4:
For more details about the PEDIU work modes, refer to section 2.8.2.1: PEDIU Control
Register (UCR)
Two additional points should be emphasized about FSCD:
1. FSCD can be used only when FSC direction is configured as output. Otherwise, if FSC
2. FSCD is designed to be sampled by external devices with DCL falling edge.
The next figure (Figure 2-33) demonstrate the behavior of FSCD, when the PEDIU
Works in Mode 2, 3 or 4 and it is not in IDLE mode, and when FSC direction is output.
:
Figure 2-33 FSCD Behavior
For more details about using FSCD, refer to Applications, section 6.
direction is configured as input, FSCD will stay in tri-state. For more details on
configuring FSC direction, refer to sections 2.10 and 2.12.3.1. When FSC is
configured as output and the PEDIU work mode is 0 or 1, or when the PEDIU is in
IDLE mode, FSCD will be driven as constant ‘0’.
DCL
(output)
FSCD
(output)
FSC with Delay (FSCD)
TS 31
last bit
32 TS with 8 subchannels.
FSCD is not used (constantly ‘0’).
64 TS with 16 subchannels.
FSCD indicates the start of time-slot 32. It is delayed by
62.5 µs relative to FSC.
128 TS with 32 subchannels.
FSCD indicates the start of time-slot 32. It is delayed by
125/4 µs (31.25 µs).
New delayed
frame
sampling
TS
1’st bit
32
TS
2’nd bit
32
2-60
Functional Block Description
ITD09691
PEB 20560
2003-08