peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 75

• Manufacturer Part Number: peb20560
• Description: Dsp Oriented Pbx Controller Doc
• Manufacturer: Infineon Technologies Corporation

One of up to 64 time-slots can be programmed independently for receive and transmit
direction via the registers TSAR and TSAX.
According to the value programmed via those bits, the receive/transmit window
(time-slot) starts with a delay of 1 (minimum delay) up to 512 clock periods following the
frame synchronization signal and is active during the number of clock periods
programmed via RCCR, XCCR (number of bits to be received/transmitted within a
time-slot) as shown in Figure 2-18.
Figure 2-18 Location of Time-Slots
Note: In extended transparent mode the width of the time-slot has to be n × 8 bit.
Clock Mode 3
In clock mode 3 SACCO-A is multiplexed among multiple subscribers under the control
of the D-channel arbiter. It must be used only in combination with transparent mode 0.
Serial data is transferred on (received from) the D-channels of the EPIC-1 IOM-2
interfaces. The data clock is derived from DCL. The D-channel arbiter generates the
receive and transmit strobes.
When bit CCR2:TXDE is set, the transmitted D-channel data can additionally be
monitored on pin TxDA delayed by 1 bit. The timing is identical to clock mode 1 assuming
a transmit strobe during the transmission of the third and fourth bit following the rising
FSC-edge.
Semiconductor Group
TSAR
TSAX
HDC
HFS
Time-Slot Number
TSN (6 Bits)
(1...512 Clocks)
1+TSNx8+CS
TSNR
TSNX
Delay
9 Bits
2-29
RCS 2
XCS 2
Clock Shift
CS (3 Bits)
(1...256 Clocks)
RCS 1
XCS 1 XCS 0
RCCR, XCCR
Time-Slot
Functional Block Description
Width
RCS 0
CCR 2
ITD05839
PEB 20560
2003-08