peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 192

• Manufacturer Part Number: peb20560
• Description: Dsp Oriented Pbx Controller Doc
• Manufacturer: Infineon Technologies Corporation

Semiconductor Group
OE
PE
FE
This bit is the Overrun Error indicator. Bit 1 indicates that data in the
receiver buffer register was not read by the µP before the next
character was transferred into the receiver buffer register, thereby
destroying the previous character. The OE indicator is set to a logic 1
upon detection of an overrun condition, and reset whenever the µP
reads the contents of the line status register. If in the FIFO mode data
continues to fill the FIFO beyond the trigger level, an overrun error
will occur only after the FIFO is full and the next character has been
completely received in the shift register. OE is indicated to the µP as
soon as it happens. The character in the shift register is overwritten,
but it is not transferred to the FIFO.
This bit is the Parity Error indicator. Bit 2 indicates that the received
data character does not have the correct even or odd parity, as
selected by the even-parity-select bit. The PE bit is set to a logic 1
upon detection of a parity error and is reset to a logic 0 whenever the
µP reads the contents of the line status register. In the FIFO mode
this error is associated with the particular character in the FIFO it
applies to. This error is revealed to the µP when its associated
character is at the top of the FIFO.
This bit is the Framing Error indicator. Bit 3 indicates that the received
character did not have a valid stop bit. Bit 3 is set to a logic 1
whenever the stop bit following the last data bit or parity bit is
detected as a logic 0 bit (spacing level). The FE indicator is reset
whenever the µP reads the contents of the line status register. In the
FIFO mode this error is associated with the particular character in the
FIFO it applies to. This error is revealed to the µP when its associated
character is at the top of the FIFO. The UART will try to resynchronize
after a framing error. To do this it assumes that the framing error was
due to the next start bit, so it samples this “start” bit twice and then
takes in the “data”.
2-146
Functional Block Description
PEB 20560
2003-08