peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 153

• Manufacturer Part Number: peb20560
• Description: Dsp Oriented Pbx Controller Doc
• Manufacturer: Infineon Technologies Corporation

TD15…0
Note: After writing an address to UPRTAR, at least 1 cycle should pass before trying to
2.8.3
2.8.3.1
The sampling of ELIC0-DD0, ELIC1-DD1 and driving ELIC0-DU0, ELIC1-DU1 by the
PEDIU must be synchronized to DCL and FSC. These two signals can be inputs to the
DOC, or can be driven by ELIC0 or ELIC1, or by the DOC’s internal clocks generator.
The PEDIU is designed to sample ELIC0-DD0 and ELIC1-DD1 in falling edges of DCL:
• In work mode 0 (IOM-2), DCL is a double data-rate clock, and the PEDIU samples the
• In work modes 1, 2, 3 and 4 the sampling occurs every DCL falling edge.
• In order to make the DD-signals sampling work correctly under these conditions, the
• The transmission of the next bit on ELIC0-DU0 and/or on ELIC1-DU1 by the PEDIU
• In work mode 0 the transmission occurs every second DCL rising edge
• In order to make the ELICs sample the DU-lines correctly, the ELICs CFI ports must
The PEDIU synchronizes its sampling of DD-lines and transmission on DU-lines by FSC
and DCL. This is done according to IOM-2 specifications, similarly to the way in which the
QUAT-S does it (see spec of the QUAT-S, PEB 2084 Version 1.2, Data Sheet 07.95,
figures 33 and 34 at pages 64-65):
• When working in PEDIU work mode 0 (double data rate DCL), PEDIU samples the
• When working in PEDIU work modes 1-4 (single data rate DCL), PEDIU samples the
Every rising edge sampling of FSC by the PEDIU starts a new PEDIU frame, and resets
its bit-counter and its time-slot counter. Reset of these counters will occur, even if the
FSC is not synchronized to the end of the former frame. In cases where the FSC rising
edge sampling is too soon and occurs before the end of the frame, the counters will be
reset, and the PEDIU starts a new frame. In such cases the output streams, which drive
the up streams into the ELIC, will not be defined during the first time-slot of the new
frame. In cases where the FSC rising edge sampling is too late, and comes after the end
of the last frame, the PEDIU will go into idle state, from the last frame end until the FSC
rising edge sampling.
Semiconductor Group
DD signals every second DCL falling edge.
ELICs CFI ports must transmit at DCL rising edge.
is done every rising edge of DCL:
be programmed to sample the DU signals at DCL falling edge.
first bit of a frame at the first falling edge of DCL after DCL falling edge, in which active
FSC was sampled, and the next samples occur every second DCL falling edge.
first bit of a frame at the same DCL falling edge, in which active FSC was sampled,
read the content of this address from UPRTDR. A nop can be placed between the
write and read instructions, in order to sustain it.
PEDIU Synchronization and Clock Rates
PEDIU Synchronization by FSC and DCL
Test Data. The PEDIU ROM content, which it’s address is consist of
UPRTAR:TA7…0, as the lsbs, and from UCR:AMUL, as the msb.
2-107
Functional Block Description
PEB 20560
2003-08