peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 387

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peb20560

Manufacturer Part Number
peb20560
Description
Dsp Oriented Pbx Controller Doc
Manufacturer
Infineon Technologies Corporation
Datasheet

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Semiconductor Group
Figure 7-16 IOM
Table 7-17 FSCD (Delayed FSC) Timing
Parameter
FSCD hold time after output
DCL falling edge
FSCD valid time after output
DCL falling edge
FSCD width
1)
When 8 MHz DCL is selected, the DSP clock rate is restricted to 40 MHz, to ensure proper work of the PEDIU.
DCL
FSC
DD
DU
DD
DU
®
-2 Interface Timing
t
FS
Symbol Limit Values Unit
t
t
t
t
FSCDH
FSCDV
FSCDW
CPL
t
t
FH
CDR
t
CP
t
1st Bit of Frame
CPH
t
1st Bit of Frame
t
t
S
CDR
FS
min.
20
900
7-26
t
H
t
t
1st Bit of Frame
FH
CDR
max.
80
150
1st Bit of Frame
2nd Bit of Frame
t
S
ns
ns
ns
ns
t
H
Electrical Characteristics
Notes
When DCL rate is
8 MHz and DSP clock
rate is 40 MHz.
When DCL rate is
4 MHz
3rd Bit of Frame
ITT10130
PEB 20560
1)
2003-08

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