peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 195

• Manufacturer Part Number: peb20560
• Description: Dsp Oriented Pbx Controller Doc
• Manufacturer: Infineon Technologies Corporation

2.14.1.5
bit
IIR
In order to provide minimum software overhead during data character transfers, the
UART prioritizes interrupts into four levels and records these in the interrupt identification
register. The four levels of interrupt conditions in order of priority are receiver line status,
received data ready, transmitter holding register empty, and modem status.
When the µP accesses the IIR, the UART freezes all interrupts and indicates the highest
priority pending interrupt to the CPU. While this µP access is occurring, the UART
records new interrupts, but does not change its current indication until the access is
complete.
Table 2-31 shows the contents of the IIR. Details on each bit follow:
Table 2-36 IIR Register
FIFO
Mode
Only
Bit 3
0
0
0
Semiconductor Group
Bit 2 Bit 1 Bit 0 Priority
0
1
1
Identification
Interrupt Identification Register (IIR)
Interrupt
Register
7
0
1
0
FE
1
0
0
6
Level
–
Highest
Second
5
0
Interrupt Set and Reset Functions
4
2-149
Interrupt
Type
None
Receiver line
status
Receiver data
available
0
3
IIDB2
Functional Block Description
Interrupt
Source
None
Overrun error
or parity error
or framing
error or break
interrupt
Receiver data
available or
trigger level
reached
2
IIDB1
1
IIDB0
Interrupt
Reset
Control
–
Reading the
line status
register
Reading the
receiver
buffer register
or the FIFO
drops below
the trigger
level
PEB 20560
0
2003-08