peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 41

• Manufacturer Part Number: peb20560
• Description: Dsp Oriented Pbx Controller Doc
• Manufacturer: Infineon Technologies Corporation

Table 1-7 Input / Output Port (cont’d)
Pin
No.
85
86
Mode 2: Additional UART Support Lines
83
Semiconductor Group
Symbol
DACKB0
HFSB0
DSR
In (I)
Out (O)
I
I
I
During
Reset
Function
DMA-ACKnowledge SACCO Channel B0,
active low.
When “low”, this line notifies the SACCO
HDLC-channel, that the requested DMA-cycle is
in progress. Together with RD (DRQR) or
WR(DRQT) DACK works like CS to enable a
read or write operation to the top of the receive
or the transmit FIFO. When DACK is active, the
address lines are ignored and the FIFOs are
implicitly selected.
When DACKB0 is not used the pin must be
connected to
HDLC-Interface Frame Synchronization SACCO
Channel B0
Frame synchronization pulse in clock mode 2,
data strobe in clock mode 1.
Data Set Ready
When low, this signal indicates that the modem
or data set is ready to establish the
communications link with the UART. The DSR
signal is a modem status input whose condition
can be tested by the CPU reading bit 5 (DSR) of
the modem status register. Bit 5 is the
complement of the DSR signal. Bit 1 (DDSR) of
the modem status register indicates whether the
DSR input has changed state since the previous
reading of the modem status register.
1-21
V
DD
.
PEB 20560
1)
Overview
2003-08