peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 312

• Manufacturer Part Number: peb20560
• Description: Dsp Oriented Pbx Controller Doc
• Manufacturer: Infineon Technologies Corporation

If the RFIFO contains less than 32 bytes (one short frame or the last bytes of a long
frame) the SACCO requests a block data transfer depending on the contents of the
RFIFO according to the following table:
Table 5-46
RFIFO Contents (bytes)
(1), 2, 3
4 - 7
8 - 15
16 - 32
Additionally an RME-interrupt is issued after the last byte has been transferred. As a
result, the DMA-controller may transfer more bytes as actually valid in the current
received frame. The valid byte count must therefore be determined reading the registers
RBCH, RBCL following the RME-interrupt.
The corresponding DRQRA/B pin remains “high” as long as the RFIFO requires data
transfers. It is deactivated upon the rising edge of the 31st DMA-transfer or, if n < 32 or n
is the remainder of a long frame, upon the falling edge of the last DMA-transfer.
If n ≥ 32 and the DMA-controller does not perform the 32nd DMA-cycle, the
DRQRA/B-line will go high again as soon as CSS goes high, thus indicating further bytes
to fetch.
5.1.1.6.2
Access: write
Reset value: xx
TD7…0
Interrupt controlled data transfer (interrupt mode, selected if DMA-bit in register
XBCH is reset).
Up to 32 bytes of transmit data can be written to the XFIFO following an XPR-interrupt.
DMA controlled data transfer (DMA-mode, selected if DMA-bit in register XBCH is set).
Prior to any data transfer, the actual byte count of the frame to be transmitted must be
written to the registers XBCH, XBCL:
Semiconductor Group
bit 7
TD7
1 byte:
n bytes:
Transmit FIFO (XFIFO)
Transmit Data 7…0, data byte to be transmitted on the serial interface.
TD6
H
XBCL = 0
XBCL = n − 1
TD5
TD4
5-69
DMA Transfers (bytes)
4
8
16
32
TD3
TD2
Description of Registers
TD1
PEB 20560
bit 0
TD0
2003-08