peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 228

• Manufacturer Part Number: peb20560
• Description: Dsp Oriented Pbx Controller Doc
• Manufacturer: Infineon Technologies Corporation

Semiconductor Group
The SACCO-A must be initialized to clock mode 3 to communicate with downstream
subscribers. In clock mode 3, the SACCO-A receives its input and transmit its output via
the D-channel arbiter. If the CCR2.T× DE-bit is set, the SACCO-A’s output is transmitted
at the T× DA-pin in addition to being transmitted via the D-channel arbiter.
Once EPIC-1 and SACCO-A have been correctly initialized, writing the subscriber’s
address into the XDC-register allows the SACCO-A to send the subscriber data. By
setting the XDC.BCT-bit and programming the BCG-registers, the SACCO-A can
transmit its data to several subscribers.
To strobe upstream data from the CFI-interface to the SACCO-A’s receiver, the AMO-
register must be programmed for the desired functionality. Subscribers who are to be
allowed to send data must be enabled via the DCE-registers. If a subscriber tries to send
data during the initialization of the upstream D-channel arbiter, a ISTA.IDA-interrupt may
occur. This interrupt can be cleared by resetting the SACCO-A receiver.
Note: 1) The EPIC-1 and SACCO-A must be initialized correctly before the D-channel
3.1.6.5
With EPIC-1, SACCO-A and D-channel arbiter all configured to the system
requirements, the PCM- and CFI-interface can be switched to the operational mode.
The OMDR:OMS1…0 bits must be set (if this has not already be done) to the normal
operation mode (OMS1…0 = 11). When doing this, the PCM-framing interrupt
(ISTA:PFI) will be enabled. If the applied clock and framing signals are in accordance
with the values programmed to the PCM-registers, the PFI-interrupt will be generated (if
not masked). When reading the status register, the STAR:PSS-bit will be set to logical 1.
To enable the PCM-output drivers set OMDR:PSB = 1. The CFI-interface is activated by
programming OMDR:CSB = 1. This enables the output clock and framing signals (DCL
and FSC), if these have been programmed as outputs. It also enables the CFI-output
drivers. The output driver type can be selected between “open drain” and “tri-state” with
the OMDR:COS-bit.
Example: Activation of the EPIC-1 part of the ELIC for a typical IOM-2 application:
OMDR = EE
arbiter can operate properly. Particular care must be given to programming the
EPIC-1’s Control Memory (CM) with the required CM-Codes (CMCs).
2) The upstream and downstream D-channel arbiter initializations are
independent of each other.
Activation of the PCM- and CFI-Interfaces
H
; Normal operation mode (OMS1…0 = 11)
PCM-interface active (PSB = 1)
PCM-test loop disabled (PTL = 0)
CFI-output drivers: open drain (COS = 1)
Monitor handshake protocol selected (MFPS = 1)
CFI active (CSB = 1)
Access to EPIC-1 registers via address pins A4…A0 (RBS = 0)
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Operational Description
PEB 20560
2003-08