peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 304

• Manufacturer Part Number: peb20560
• Description: Dsp Oriented Pbx Controller Doc
• Manufacturer: Infineon Technologies Corporation

Note: In extended transparent mode 0 and 1 the bit MODE:RAC must be reset to enable
CFT
RAC
TLP
5.1.1.5.8
Access: read/write
Reset value: 00
PU
CM2
Semiconductor Group
bit 7
PU
fully transparent reception.
Channel Configuration Register 1 (CCR1)
• Transparent mode
• Extended transparent mode
Continuous Frame Transmission.
1…When CFT is set the XPR-interrupt is generated immediately after the
0…Otherwise the XPR-interrupt is delayed until the transmission is
Receiver Active.
Via RAC the HDLC-receiver can be activated/deactivated.
0…HDLC-receiver inactive
1…HDLC-receiver active
In extended transparent mode 0 and 1 RAC must be reset (HDLC-receiver
disabled) to enable fully transparent reception.
Test Loop.
When set input and output of the HDLC-channel are internally connected.
(transmitter channel A - receiver channel A
transmitter channel B - receiver channel B)
TXDA/B are active, RXDA/B are disabled.
Power-Down Mode.
0…power-down (standby), the internal clock is switched off. Nevertheless,
1…power-up (active).
Clock rate
0…single clock
1…double clock
0…no address recognition: transparent mode 0 (D-channel arbiter)
1…high byte address recognition: transparent mode 1
0…receive data in RAL1: extended transparent mode 0
1…receive data in RFIFO and RAL1: extended transparent mode 1
register read/write access is possible.
CPU accessible part of XFIFO is copied into the transmitter section.
completed (D-channel arbiter).
H
0
0
0
5-61
0
CM2
Description of Registers
1
PEB 20560
bit 0
2003-08
1