peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 238

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peb20560

Manufacturer Part Number
peb20560
Description
Dsp Oriented Pbx Controller Doc
Manufacturer
Infineon Technologies Corporation
Datasheet

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4.2
4.2.1
• 16-bit fixed-point DSP CORE with high level of modularity:
• 16 × 16 bit 2’s complement parallel multiplier with 32-bit product. Multiplication of
• Single cycle multiply-accumulate instructions.
• 36-bit ALU.
• 36-bit left/right Barrel Shifter.
• Four 36-bit accumulators.
• Memory organization:
• 64 K word maximum addressable data space, organized in:
• Software stack (with stack pointer) residing in the data RAM.
• Index-based addressing capability.
• Automatic context switching by interrupts (with enable/disable feature for each
• All general and most special purpose registers are arranged as a global register set
• Bit-Field (up to 16 bits) Operations (BFO): Set, Reset, Change, Test.
• Single cycle exponent evaluation of up to 36-bit values.
• Enables full normalization operation in 2 cycles.
• Double precision multiplication support.
• Max/Min single cycle instruction with pointer latching and modification.
• Single cycle Division step support.
• Single cycle data move & shift capability.
• Arithmetic and logical shifting capability, according to a shift value stored in a special
Semiconductor Group
signed by signed, signed by unsigned, and unsigned by unsigned.
local and external data memory space.
– 64 K word maximum program memory space.
– Data RAMs can also be viewed as a single continuous RAM.
– User definable data ROM on the same address space of the data RAM.
– Alternative registers bank for 3 of the DAAU pointers (and 1 configuration register)
interrupt) using Shadow registers for parts of status registers and swapping between
two 36-bit accumulators.
of 34 registers that can be referenced in most data moves and core operations.
These operations are executed directly on registers and data memory content, with
no affect on accumulators’ content.
Optimized for codebook search and Viterbi decoding.
register, or embedded in the instruction opcode. Conditional shift is also available, as
well as rotate left and right operations.
– Expandable internal program ROM.
– Expandable internal data RAM and/or ROM.
– User-defined registers.
with individual selectable bank exchanging.
Architecture Features
Features
4-3
DSP Core OAK
PEB 20560
2003-08

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