peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 194

• Manufacturer Part Number: peb20560
• Description: Dsp Oriented Pbx Controller Doc
• Manufacturer: Infineon Technologies Corporation

Semiconductor Group
2.14.1.4
bit
FCR
This is a write only register at the same address location as the IIR (the IIR is a read only
register). This register is used to enable the FlFOs, clear the FlFOs, set the RCVR FIFO
trigger level, and select the type of DMA signaling.
FEWO
RFR
TFR
DMS
Bit 4 and 5
FCR7:6
FIFO Control Register (FCR)
7
FCR7
Writing a 1 to FEWO enables both the XMIT and RCVR FlFOs.
Resetting FEWO will clear all bytes in both FlFOs. When changing
from FIFO mode to 16450 mode and vice versa, data is automatically
cleared from the FlFOs. This bit must be a 1 when other FCR bits are
written to, or they will not be programmed.
Writing a 1 to RFR clears all bytes in the RCVR FIFO and resets its
counter logic to 0. The shift register is not cleared. The 1 that is
written to this bit position is self-clearing.
Writing a 1 to TFR clears all bytes in the XMIT FIFO and resets its
counter logic to 0. The shift register is not cleared. The 1 that is
written to this bit position is self-clearing.
Setting DMS to a 1 will cause the RXRDY and TXRD pins to change
from mode 0 to mode 1 if FEWO = 1 (see description of RXRDY and
TXRDY pins).
These bits are reserved for future use.
FCR6 and FCR7 are used to set the trigger level for the RCVR FIFO
interrupt.
Bit 7
0
0
1
1
6
FCR6
5
Bit 6
0
1
0
1
2-148
4
3
DMS
RCVR FIFO
Trigger Level (Bytes)
01
04
08
14
Functional Block Description
2
TFR
1
RFR
PEB 20560
0
FEWO
2003-08