peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 213

• Manufacturer Part Number: peb20560
• Description: Dsp Oriented Pbx Controller Doc
• Manufacturer: Infineon Technologies Corporation

PEB 20560
Operational Description
CFI - PCM Time-Slot Assignment
Switching paths 1 and 2 of Figure 3-2 can be realized for a total number of 128 channels
per path, i.e. 128 time-slots in upstream and 128 time-slots in downstream direction. To
establish a connection, the µP writes the addresses of the involved CFI and PCM
time-slots to the control memory. The actual transfer is then carried out frame by frame
without further µP-intervention.
The switching paths 5 and 6 can be realized by programming time-slot assignments in
the control memory. The total number for such loops is limited to the number of available
time-slots at the respective opposite interface, i.e. looping back a time-slot from CFI to
CFI requires a spare upstream PCM time-slot and looping back a time-slot from PCM to
PCM requires a spare downstream and upstream CFI time-slot.
time-slot switching is always carried out on 8-bit time-slots, the actual position and
number of transferred bits can however be limited to 4-bit or 2-bit sub time-slots within
these 8-bit time-slots. On the CFI-side, only one sub time-slot per 8-bit time-slot can be
switched, whereas on the PCM-interface up to 4 independent sub time-slots can be
switched.
Sub Time-Slot Switching
Sub time-slot positions at the PCM-interface can be selected at random, i.e. each single
PCM time-slot-may contain any mixture of 2- and 4-bit sub time-slots. A PCM time-slot
may also contain more than one sub time-slot. On the CFI however, two restrictions must
be observed:
– Each CFI time-slot may contain one and one only sub time-slot.
– The sub-slot position for a given bandwidth within the time-slot is fixed on a per port
basis.
µP-Transfer
Switching paths 3 and 4 of Figure 3-2 can be realized for all available time-slots. Path 3
can be implemented by defining the corresponding CFI time-slots as “µP-channels” or
as “pre-processed channels”.
Each single time-slot can individually be declared as “µP-channel”. If this is the case,
the µP can write a static 8-bit value to a downstream time-slot which is then transmitted
repeatedly in each frame until a new value is loaded. In upstream direction, the µP can
read the received 8-bit value whenever required, no interrupts being generated.
The “pre-processed channel” option must always be applied to two consecutive
time-slots. The first of these time-slots must have an even time-slot number. If two time-
slots are declared as “pre-processed channels”, the first one can be accessed by the
monitor/feature control handler, which gives access to the frame via a 16-byte FIFO.
Although this function is mainly intended for IOM- or SLD-applications, it could also be
used to transmit or receive a “burst” of data to or from a 64-kbit/s channel. The second
Semiconductor Group
3-7
2003-08