peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 313

• Manufacturer Part Number: peb20560
• Description: Dsp Oriented Pbx Controller Doc
• Manufacturer: Infineon Technologies Corporation

Semiconductor Group
If a data transfer is then initiated via the CMDR-register (commands XPD/XTF or XDD),
the SACCO autonomously requests the correct amount of block data transfers (n × 32 +
remainder, n = 0,1, …).
The corresponding DRQTA/B pin remains “high” as long as the XFIFO requires data
transfers. It is deactivated upon the rising edge of WR in the DMA-transfer 31 or n − 1
respectively. The DMA-controller must take care to perform the last DMA-transfer. If it is
missing, the DRQTA/B-line will go active again when CSS is raised.
5.1.1.6.3
Access: read
Reset value: 00
RME
RPF
Note: This interrupt is only generated in interrupt mode (not in DMA-mode).
XPR
5.1.1.6.4
Access: write
Reset value: 00
RME
RPF
bit 7
bit 7
RME
RME
Interrupt Status Register (ISTA_A/B)
Mask Register (MASK_A/B)
Receive Message End.
A message of up to 32 bytes or the last part of a message greater then
32 bytes has been received and is now available in the RFIFO. The
message is complete! The actual message length can be determined by
reading the registers RBCL, RBCH. RME is not generated when an
extended HDLC- frame is recognized in auto-mode (EHC interrupt).
In DMA-mode a RME-interrupt is generated after the DMA-transfer has been
finished correctly, indicating that the processor should read the registers
RBCH/RBCL to determine the correct message length.
Receive Pool Full.
A data block of 32 bytes is stored in the RFIFO. The message is not yet
completed!
Transmit Pool Ready.
A data block of up to 32 bytes can be written to the XFIFO.
enables(0)/disables(1) the Receive Message End interrupt.
enables(0)/disables(1) the Receive Pool Full interrupts.
RPF
RPF
H
H
(all interrupts enabled)
0
0
XPR
XPR
5-70
0
0
0
0
Description of Registers
0
0
PEB 20560
bit 0
bit 0
2003-08
0
0