peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 320

• Manufacturer Part Number: peb20560
• Description: Dsp Oriented Pbx Controller Doc
• Manufacturer: Infineon Technologies Corporation

XCS0
RCS0
Note: In the clock modes 0,1 and 3 XCS0 and RCS0 has to be set to '0'.
TXDE
RDS
Note: With RDS = 1 the sampling edge is shifted 1/2 clock phase forward. The data is
RIE
5.1.1.6.10 Receive Length Check Register (RLCR)
Access: write
Reset value: 0xxxxxxx
RC
RL6…0
Semiconductor Group
bit 7
RC
internally still processed with the falling edge.
• Point-to-point configuration:
Transmit/receive Clock Shift, bit 0 (only clock mode 2).
Together with the bits XCS2, XCS1 (RCS2, RCS1) in TSAX (TSAR) the
clock shift relative to the frame synchronization signal of the transmit
(receive) time-slot can be adjusted. A clock shift of 0…7 bits is
programmable (clock mode 2 only!).
Transmit Data Enable.
0…the pin TxDA/B is disabled (in the state high impedance).
1…the pin TxDA/B is enabled. Depending on the programming of bit
Receive Data Sampling.
0 : serial data on RXDA/B is sampled at the falling edge of HDCA/B.
1 : serial data on RXDA/B is sampled at the rising edge of HDCA/B.
Receive frame start Enable.
When set, the RFS-interrupt in register EXIR_A/B is enabled.
Receive Check enable.
A ‘1’ enables, a ‘0’ disables the receive frame length feature.
Receive Length.
The maximum receive length after which data reception is suspended can
be programmed in RL6…0. The maximum allowed receive frame length is
(RL + 1) × 32 bytes. A frame exceeding this length is treated as if it was
aborted by the opposite station (RME-interrupt, RAB-bit set (VFR in clock
mode 3)).
RL6
11…the TSCA/B-output indicates the reception of a data frame (active
0x…the TSCA/B-output is activated during the transmission of a frame.
1x…the TSCA/B-output is activated during the transmission of a frame
CCR1:ODS it has a push pull or open drain characteristic.
and of inter frame timefill.
low)
H
RL5
RL4
5-77
RL3
RL2
Description of Registers
RL1
PEB 20560
bit 0
RL0
2003-08