peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 227

• Manufacturer Part Number: peb20560
• Description: Dsp Oriented Pbx Controller Doc
• Manufacturer: Infineon Technologies Corporation

Depending on the features desired, the following registers may also require initializing
before powering up the SACCO:
Table 3-4 Feature Dependent Register Set-up
Feature
Clock mode 2
Masking selected interrupts
DMA controlled data transfer
Check on receive length
The CCR1 is the final minimum register that has to be programmed to initialize the
SACCO. In addition to defining the serial port configuration, the CCR1 sets the clock
mode and allows the CPU to power-up or power-down the SACCO.
In power-down mode all internal clocks are disabled, and no interrupts are forwarded to
the CPU. This state can be used as standby mode for reduced power consumption.
Switching between power-up or power-down mode has no effect on the contents of the
register, i.e. the internal state remains stored.
After power-up of the SACCO, the CPU should bring the transmitter and receiver to a
defined state by issuing a XRES (transmitter reset) and RHR (receiver reset) command
via the CMDR-register. The SACCO will then be ready to transmit and receive data.
The CPU controls the data transfer phase mainly by commands to the SACCO via the
CMDR-register, and by interrupt indications from the SACCO to the CPU. Status
information that does not trigger an interrupt is constantly available in the STAR-register.
3.1.6.4
The D-channel arbiter links the SACCO-A to the CFI of the EPIC-1 part of the ELIC. Thus
the EPIC-1 and SACCO-parts of the ELIC should be initialized before initializing the
D-channel arbiter.
For subscribers wishing to communicate with the SACCO-A, the correct pre-processed
channel code must have been programmed in the EPIC-1’s control memory. In
downstream direction, this code is CMC = 1010 for the even time-slot and CMC = 1011
for the odd time-slot. In upstream direction, any pre-processed channel code is also valid
for arbiter operation. This is shown in Figure 3-3 of chapter 3.1.3.3. For an example
refer to chapter 3.1.6.2.3.
If the MR-bit is used to block downstream subscribers, the blocking code MR = ‘0’
be written as MADR = ‘11xxxx01’
‘x’ stand for the C/I-code. This also is shown in Figure 3-3.
If the C/I-code is used to block downstream subscribers, such subscribers must be
activated with the C/I-code ‘1100’
Semiconductor Group
Initialization of D-Channel Arbiter
B
B
, not ‘1000’
when initializing the even downstream time-slot. The
3-21
Register(s)
TSAR, TSAC, XCCR, RCCR
MASK
XBCH
RLCR
B
.
Operational Description
PEB 20560
2003-08
B
can