peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 223

• Manufacturer Part Number: peb20560
• Description: Dsp Oriented Pbx Controller Doc
• Manufacturer: Infineon Technologies Corporation

3.1.6
For proper initialization of the DOC the following procedure is recommended:
3.1.6.1
Refer to chapter 2.1.2.2 “Reset Logic”.
3.1.6.2
3.1.6.2.1
The PCM- and CFI-configuration registers (PMOD, PBNR, … , CMD1, CMD2, … ) should
be programmed to the values required for the application. The correct setting of the
PCM- and CFI-registers is important in order to obtain a reference clock (RCL) which is
consistent with the externally applied clock signals.
The state of the operation mode (OMDR:OMS1…0 bits) does not matter for this
programming step.
3.1.6.2.2
Since the hardware reset does not affect the EPIC-1 memories (Control and Data
Memories), it is mandatory to perform a “software reset” of the CM. The CM-code ‘0000’
(unassigned channel) should be written to each location of the CM. The data written to
the CM-data field is then don’t care, e.g. FF
OMDR:OMS1…0 must be to ‘00’
The resetting of the complete CM takes 256 RCL-clock cycles. During this time, the
EPIC.STAR:MAC-bit is set to logical 1.
Semiconductor Group
PMOD =
PBNR
POFD
POFU
PCSR
CMD1
CMD2
CBNR
CTAR
CBSR
CSCR
MADR =
MACR =
Wait for EPIC.STAR:MAC = 0
Initialization Procedure
Hardware Reset
EPIC
EPIC
Control Memory Reset
=
=
=
=
=
=
=
=
=
=
®
®
-1 Initialization
Registers Initialization
PCM-mode, timing characteristics, etc.
Number of bits per PCM-frame
PCM-offset downstream
PCM-offset upstream
PCM-timing
CFI-mode, timing characteristics, etc.
CFI-timing
Number of bits per CFI-frame
CFI-offset (time-slots)
CFI-offset (bits)
CFI-sub channel positions
FF
70
H
H
B
for this procedure (reset value).
3-17
H
.
Operational Description
PEB 20560
2003-08