peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 298

• Manufacturer Part Number: peb20560
• Description: Dsp Oriented Pbx Controller Doc
• Manufacturer: Infineon Technologies Corporation

PSB
PTL
COS
MFPS
CSB
RBS
Semiconductor Group
PCM-Standby.
0…the PCM-interface output pins TxD0…3 are set to high impedance and
1…the PCM-output pins transmit the contents of the upstream data memory
PCM-Test Loop.
0…the PCM-test loop is disabled.
1…the PCM-test loop is enabled, i.e. the physical transmit pins TxD# are
Don’t care. The input driver is determinated in register CCR1:ODS of
SIDEC0.
Monitor/Feature control channel Protocol Selection.
0…handshake facility disabled (SLD and IOM-1 applications)
1…handshake facility enabled (IOM-2 applications)
CFI-Standby.
0…the CFI-interface output pins DD0…3, DU0…3, DCL and FSC are set to
1…the CFI-output pins are active.
Register Bank Selection. Used in demultiplexed data/address modes only.
The RBS-bit is internally ORed with the A4 address pin. The EPIC-1
registers can therefore be accessed using two different methods:
1) If RBS is always set to logical 0, the registers can be accessed using
those TSC-pins that are actually used as tri-state control signals are set
to logical 1 (inactive).
or may be set to high impedance via the data memory tri-state field.
internally connected to the corresponding physical receive pins RxD#,
such that data transmitted over TxD# are internally looped back to RxD#
and data externally received over RxD# are ignored. The TxD# pins still
output the contents of the upstream data memory according to the
setting of the tri-state field (only modes 0 and 1; mode 1 with AIS-bit set).
high impedance.
all 5 address pins A4…A0.
5-55
Description of Registers
PEB 20560
2003-08