tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 118

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

3.6
External Bus Interface
I/Os which are external to the chip. This function is implemented by the external bus interface circuit (EBIF)
and the CS (chip select)/wait controller.
and data bus width (8 bits or 16 bits) for these four address spaces and other external address spaces.
the CS/wait controller. The EBIF also controls dynamic bus sizing and the arbitration of bus contention with
external bus masters.
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The TMP1942 contains an external bus interface function which is necessary for connecting memory or
The CS/wait controller specifies mapping addresses for any four address spaces, and controls a wait state
The external bus interface circuit (EBIF) controls timing for the external bus based on settings made with
Wait function
Data bus width
Read recovery cycle
clock cycles can be inserted.
Control of ALE width
Arbitration of bus contention
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Can be set individually for each block.
The bus width can be independently selected as 8 bits or 16 bits for each block.
When a external bus cycle is immediately followed by a next external bus cycle, up to two dummy
Insertion of the dummy cycle(s) can be set individually for each block.
The ALE width can be set to 0.5 or 1.5 clock cycles.
The set ALE width applies to all blocks in common.
A wait state of up to 7 clock cycles can be automatically inserted.
Wait states can be inserted from the
TMP1942CY/CZ-117
WAIT
pin.
TMP1942CY/CZ