tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 191

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

3.
External
pins
Register
name
(address)
3.10 16-Bit Timers/Event Counters (TMRBn)
Specification
External clock/
capture trigger input pins
Capture trigger timer
Timer flip-flop output pin
Timer run register
Timer mode register
Timer flip-flop control
register
Timer registers
Capture registers
TMRBn can operate in the following four modes:
•
•
•
•
modes:
•
•
•
structure), two 16-bit capture registers, two comparators, capture input controller, and a timer flip-flop with
accompanying control circuit. Timer operating modes and flip-flops are controlled by eleven registers.
same way except for the 2-phase pulse counter function and a few other differences as shown in Tables 3.10.1
to 3.10.2, operation of the TMRB0 only is described here, with an explanation of the 2-phase pulse counter
function for TMRB2 and TMRB3.
The TMP1942 contains fourteen multi-function 16-bit timer/event counter channels (TMRB0-TMRBD).
In addition, when used in combination with the capture function, TMRBn can be run in the following
Each channel consists primarily of a 16-bit up-counter, two 16-bit timer registers (one with a double-buffer
All channels TMRB0 to TMRBD operate independently of each other. Because each channel functions the
16-bit interval timer mode
16-bit event counter mode
16-bit programmable square wave output (PPG) mode
2-phase pulse input counter mode (only for TMRB2 and TMRB3)
Frequency measurement mode
Pulse width measurement mode
Time difference measurement mode
Table 3.10.1 Specification Differences Among the TMRB Channels
TB0IN0 (Shared with PA0)
TB0IN1 (Shared with PA1)
TA3OUT
TB0OUT (Shared with PA2) TB1OUT (Shared with PA5) TB2OUT (Shared with PB2) TB3OUT (Shared with PB5)
TB0RUN (0xFFFF_F140)
TB0MOD (0xFFFF_F142)
TB0FFCR (0xFFFF_F143)
TB0RG0L (0xFFFF_F148)
TB0RG0H (0xFFFF_F149)
TB0RG1L (0xFFFF_F14A)
TB0RG1H (0xFFFF_F14B)
TB0CP0L (0xFFFF_F14C)
TB0CP0H (0xFFFF_F14D)
TB0CP1L (0xFFFF_F14E)
TB0CP1H (0xFFFF_F14F)
TMRB0
TMP1942CY/CZ-190
TB1IN0 (Shared with PA3)
TB1IN1 (Shared with PA4)
TA3OUT
TB1RUN (0xFFFF_F150)
TB1MOD (0xFFFF_F152)
TB1FFCR (0xFFFF_F153)
TB1RG0L (0xFFFF_F158)
TB1RG0H (0xFFFF_F159)
TB1RG1L (0xFFFF_F15A)
TB1RG1H (0xFFFF_F15B)
TB1CP0L (0xFFFF_F15C)
TB1CP0H (0xFFFF_F15D)
TB1CP1L (0xFFFF_F15E)
TB1CP1H (0xFFFF_F15F)
TMRB1
Channel
TB2IN0 (Shared with PB0)
TB2IN1 (Shared with PB1)
TA3OUT
TB2RUN (0xFFFF_F160)
TB2MOD (0xFFFF_F162)
TB2FFCR(0xFFFF_F163)
TB2RG0L (0xFFFF_F168)
TB2RG0H (0xFFFF_F169)
TB2RG1L (0xFFFF_F16A)
TB2RG1H (0xFFFF_F16B)
TB2CP0L (0xFFFF_F16C)
TB2CP0H (0xFFFF_F16D)
TB2CP1L (0xFFFF_F16E)
TB2CP1H (0xFFFF_F16F)
TMRB2
TX1942CY/CZ
TB3IN0 (Shared with PB3)
TB3IN1 (Shared with PB4)
TA3OUT
TB3RUN (0xFFFF_F170)
TB3MOD (0xFFFF_F172)
TB3FFCR (0xFFFF_F173)
TB3RG0L (0xFFFF_F178)
TB3RG0H (0xFFFF_F179)
TB3RG1L (0xFFFF_F17A)
TB3RG1H (0xFFFF_F17B)
TB3CP0L (0xFFFF_F17C)
TB3CP0H (0xFFFF_F17D)
TB3CPIL (0xFFFF_F17E)
TB3CPIH (0xFFFF_F17F)
TMRB3