tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 275

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Timing at which received
data is written to buffer
SCLK0 input
(SCLKS =0: Rise mode)
SCLK0 input
(SCLKS =1: Fall mode)
RXD0
(INTRX0 interrupt request)
RBFULL
Timing at which received
data is written to buffer
SCLK0 input
(SCLKS =0: Rise mode)
SCLK0 input
(SCLKS =1: Fall mode)
RXD0
(INTRX0 interrupt request)
RBFULL
OERR
Note: Before receive operation can be performed in either SCLK input mode or SCLK output mode,
reception must be enabled by setting SC0MOD<RXE> to 1.
Figure 3.11.39 Receive Operation in I/O Interface Mode (SCLK0 Input Mode)
3)
transferred to receive buffer 2, so that receive buffer 1 can receive the next frame immediately.
occurs.
Transmission/reception (full-duplex)
output mode, writing data to the transmit buffer initiates SCLK output and shifts the received
8-bit data into receive buffer 1, generating a receive interrupt (INTRX0). Simultaneously, the
8-bit data written to the transmit buffer is output on the TXD0 pin. When all bits of data have
been transmitted, a transmit interrupt (INTTX0) is generated, causing SCLK output to stop.
When the CPU subsequently reads the receive buffer and writes data to the transmit buffer,
next transmission/reception starts. Transmission/reception is restarted when the CPU has
performed both the read and write, regardless of their sequence.
In SCLK input mode, the receive double-buffer is always enabled. The received frame is
Each time received data has been transferred to receive buffer 2, an INTRX0 interrupt
Setting SC0MOD1<FDPX0> to 1 enables full-duplex communication.
If WBUF = 0, that is, both the transmit and receive double-buffers are disabled in SCLK
bit 0
bit 0
TMPR1942CY/CZ-274
If data is read from buffer 2
bit 1
bit 1
bit 5
bit 5
bit 6
bit 6
TMP1942 CY/CZ
bit 7
bit 7
bit 0
bit 0