tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 370

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

SIO Timing
SCLK period
TxD data to SCLK rise or fall
TxD data hold after SCLK rise or fall*
RxD data valid to SCLK rise or fall*
RxD data hold after SCLK rise or fall*
SCLK period
TxD data to SCLK rise or fall
TxD data hold after SCLK rise or fall*
RxD data valid to SCLK rise or fall*
RxD data hold after SCK rise
(1) I/O Interface Mode
Note *: SCLK rise or fall: Measured relative to the programmed active edge of SCLK.
SIO5(DVCC51=2.7V~3.6V or 4.5V~5.25V)
programming of the clock gear function.
1. SCLK Input Mode(SIO0,SIO1,SIO3,SIO4)
Parameter
Parameter
In the tables below, the letter x represents the fsys cycle period, which varies, depending on the
Sym
t
t
t
t
t
Sym
t
t
t
t
t
SCY
OSS
OHS
SRD
HSR
SCY
OSS
OHS
SRD
HSR
bol
bol
TMP1942CY/CZ-369
(t
(t
SCY
SCY
(t
(t
SCY
SCY
/2) − 5x − 23
/2) − 5x − 23
2x + 8
2x + 8
Min
Min
16x
16x
/2) + 3x
/2) + 3x
Equation
Equation
0
0
Max
Max
Min
Min
800
127
550
108
800
127
550
108
0
0
20 MHz
20 MHz
Max
Max
TMP1942CY/CZ
Min
Min
500
343
500
343
72
70
72
70
0
0
32 MHz
32 MHz
Max
Max
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns