tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 342

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

INTBST
(0xFFFF_F380) Read/Write
INTCST
(0xFFFF_F381) Read/Write
INTDST
(0xFFFF_F382) Read/Write
3.16 INTB, INTC, INTD, INTE
internally ORed and the result is input to the CG and INTC. Therefore, they represent a single interrupt source.
You can determine which interrupt has actually occurred by checking the corresponding bits of INTFLG.
These flags are cleared when read.
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The TMP1942 supports extended interrupts INTB, INTC, INTD and INTE. These four interrupts are
Can be used to terminate STOP/SLEEP mode (wake-up) or as an external interrupt. When used for
wake-up, all four interrupts must be set collectively (in the CG block). Whether individual pins are used
or not used can be specified separately (INTnST).
A single interrupt source is available (INTBCDE).
Rising edge, falling edge, High level, or Low level detection can be selected for individual inputs
(INTnST).
The interrupt source is cleared by reading INTFLG in the interrupt handling routine.
Which interrupt has occurred can be determined using the INTFLG register.
Bit symbol
After Reset
Function
Bit symbol
After Reset
Function
Bit symbol
After Reset
Function
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
7
7
7
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
6
6
6
TMP1942CY/CZ-341
Sets INTB active
condition
00: Low level
01: High level
10: Falling edge
11: Rising edge
Sets INTC active
condition
00: Low level
01: High level
10: Falling edge
11: Rising edge
Sets INTD active
condition
00: Low level
01: High level
10: Falling edge
11: Rising edge
INTB1
INTC1
INTD1
5
5
5
1
1
1
R/W
R/W
R/W
INTB0
INTC0
INTD0
4
4
4
0
0
0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
3
3
3
TMP1942CY/CZ
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
2
2
2
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
1
1
1
INTB
interrupt
input
0: Disable
1: Enable
INTC
interrupt
input
0: Disable
1: Enable
INTD
interrupt
input
0: Disable
1: Enable
INTCEN
INTDEN
INTBEN
R/W
R/W
R/W
0
0
0
0
0
0