tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 352

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

3.19.2
(2) Watchdog timer control register (WDCR)
Control Registers
(1) Watchdog timer mode register (WDMOD)
The watchdog timer (WDT) can be controlled using two control registers (WDMOD and WDCR).
a. Setting the watchdog timer detection time (WDTP1:WDTP0)
b. Enabling/disabling the watchdog timer (WDTE)
c. Connecting the watchdog timer output to reset (RESCR)
Note: Writing the disable code (B1H) causes the binary counter to be cleared.
runaway condition. Upon a
WDMOD<RESCR> = 0, the CPU will not be reset by the watchdog timer output.
the binary counter.
•
disable code (B1H) to the WDCR register.
a runaway condition. Upon a reset, WDMOD<WDTP1:WDTP0> are initialized to 00. Figure
3.19.4 shows watchdog timer detection times.
to the WDCR register. This dual setting ensures that the watchdog timer cannot easily be disabled
by a runaway condition.
to 1.
•
•
counting.
These two bits are used to set the watchdog timer interrupt detection time necessary for detecting
Upon a reset, WDMOD<WDTE> is initialized to 1, enabling the watchdog timer.
To disable the watchdog timer, set this bit to 0 and, at the same time, write the disable code (B1H)
To re-enable the watchdog timer after it has been disabled, simply set the WDMOD<WDTE> bit
This bit is used to specify whether or not the CPU itself will be reset upon the detection of a
This register controls the watchdog timer by disabling the watchdog timer function and clearing
The watchdog timer can be disabled by setting WDMOD<WDTE> to 0 and then writing the
Set WDMOD<WDTE> to 1.
Writing the clear code (4EH) to the WDCR register clears the binary counter and restarts
Disabling the watchdog timer
Enabling the watchdog timer
Clearing the binary counter
WDMOD
WDCR
WDCR
← 0 − − − − − − −
← 1 0 1 1 0 0 0 1
← 0 1 0 0 1 1 1 0
TMP1942CY/CZ-351
reset,
WDMOD<RESCR>
Clear WDTE to 0.
Write clear code (4EH).
Write disable code (B1H).
TMP1942CY/CZ
is initialized to
0. When