tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 16

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

3.
3.1
3.1.1
Functional Description
devices.
Recommended power-on sequence:
In powering up this device, it is recommended that the DVCC3 be turned on first.
At power-on, the pull-up resistors and input & output buffers pull-down resistors attached to
the I/O ports of the 5V supply domain may rail become unstable or a through current may pass
through the port until the DVCC3 has stabilized, when an injection order is not kept.
This section describes the functions and basic operation of each individual circuit block in the TMP1942 series
Processor Core
the operation of the processor core, refer to “TX19 Family Architecture”.
below.
The TX1942 contains a high-performance 32-bit processor core (the TX19 processor core). For details of
Functions unique to the TMP1942, which are not explained in “TX19 Family Architecture”, are described
Reset Operation
power supply voltage is within the rated operating range and the internal high-frequency oscillator is
oscillating stably. (With the device operating at 32 MHz, this period is equal to 3 μs if the PLL is being
used and 6 μs if the PLL is not being used.) After a reset the PLL-multiplied clock is specified by the
setting of the PLLOFF pin and the clock gear is initialized to 1/8 mode.
supply voltage and the internal high-frequency oscillator have stabilized. This time is typically 3 μs at 32
MHz when the on-chip PLL is utilized, and 6μs otherwise. After a reset, either the PLL-multiplied clock
or an external clock is selected, depending on the logic state of the PLLOFF pin. By default, the selected
clock is geared down to 1/8 for internal operation.
To reset the TMP1942, RESET must be input Low (at 0) for at least 12 system clock cycles while the
The following occurs as a result of a reset:
To reset the TMP1942, RESET must be asserted for at least 12 system clock periods after the power
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The System control coprocessor (CP0) registers within the TX19 core processor are initialized.
For details, refer to the Architecture manual.
The Reset exception is taken. Program control is transferred to the exception handler at a
predefined address. This predefined location is called an exception vector, which directly
indicates the start of the actual exception handler routine. The Reset exception is always
vectored to virtual address 0xBFC0_0000 (which is the same as for the Nonmaskable Interrupt
exception).
All on-chip I/O peripheral registers are initialized.
All port pins, including those multiplexed with on-chip peripheral functions, are configured as
either general-purpose inputs or general-purpose outputs.
TMP1942CY/CZ-15
TMP1942CY/CZ