tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 388

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

6.3 JTAG Controller and Registers
6.3.1
testing.
When it occurs, the TAP controller determines the test functionality to be implemented. This includes either
loading the JTAG instruction register (IR), or beginning a serial data scan through a data register (DR), listed in
Table 6.3.1. As the data is scanned in, the state of the JTMS pin signals each new data word, and indicates the
end of the data stream. The data register to be selected is determined by the contents of the Instruction register.
The processor contains the following JTAG controller and registers:
The processor executes the standard JTAG EXTEST operation associated with External Test functionality
The basic operation of JTAG is for the TAP controller state machine to monitor the JTMS input signal.
Instruction Register
•
•
•
•
•
test to be performed and/or the test data register to be accessed. As listed in Table 6.3.1, this encoding
selects either the Boundary-scan register or the Bypass register or Device Identification register.
Instruction Code
TDI
The JTAG Instruction register includes eight shift register-based cells; this register is used to select the
Figure 66.3.1 shows the format of the Instruction register
The instruction code is shifted out to the Instruction register from the LSB.
(MSB → LSB)
Instruction register
Boundary-scan register
Bypass register
ID Code register
Test Access Port (TAP) controller
0010 to 1110
0000
0001
1111
MSB
3
Table 6.3.1 JTAG Instruction Register Bit Encoding
Figure 6.3.2 Instruction Register Shift Direction
MSB
Figure 66.3.1 Instruction Register
SAMPLE/PRELOAD
TMP1942CY/CZ-387
2
Instruction
Reserved
BYPASS
EXTEST
1
Selected Data Register
LSB
Boundary Scan Register
Boundary Scan Register
Bypass register
Reserved
TMP1942CY/CZ
LSB
0
TDO