tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 152

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Note1: The NMI interrupt is left pending while the DMAC has control of the bus.
Note2: Do not place the TMP1962 in Halt power-down mode while the DMAC is operating.
(2) Switching control of the bus (bus arbitration)
(3) Transfer request modes
(4) Address modes
control of the bus from the TX19 processor core. If an acknowledge signal is returned by the
TX19 processor core, the DMAC gains control of the bus and can perform data transfer bus
cycles.
processor core’s data bus (i.e., the snoop function), or bus control without the snoop function.
This can be set independently for each channel in the corresponding register.
DMAC should respond to this request is set using independent register settings for each
channel. However, this response function is effective only when the DMAC does not request
the snoop function (i.e., in GREQ mode). When the snoop function is requested (i.e., in SREQ
mode), the response function will have no effect because the TX19 processor core cannot
generate requests for release of bus control in this mode.
transfer request mode.
transfer request is generated by setting the start bit in one of the DMAC’ s internal registers (the
channel control register’s Str bit) to 1, upon which the DMAC will start a transfer operation.
request signal (INTDREQn), which is output by the interrupt controller after the start bit has
been set to 1. The DMAC can select level mode, in which a transfer request is generated on
detection of a High- or Low-level INTDREQn signal, or edge mode, in which a transfer request
is generated on detection of the rising or falling edge of the INTDREQn signal. However,
because the INTDREQn signal in the TMP1942 is low-active, always make sure that the
transfer request signal is set to be detected at Low level.
There is no single-address mode for the DMAC.
memory and an I/O device. The addresses of the source and destination devices are output by
the DMAC. When accessing an I/O device, the DMAC asserts the DACKn signal. In
dual-address mode, the DMAC executes two bus operations, one for reading and one for
writing. The transfer data read from the source device is temporarily stored in the DMAC’s
internal data-holding register (DHR) before being written to the destination device.
When a transfer request is issued by the DMAC’s internal circuitry, the DMAC requests
The DMAC can request two types of bus control: either bus control plus the use of the TX19
The TX19 processor core may request release of bus control from the DMAC. Whether the
When there are no more transfer requests, the DMAC will finish control of the bus.
The DMAC has two transfer request modes: internal transfer request mode and external
In internal transfer request mode, transfer requests are generated internally in the DMAC. A
In external transfer request mode, transfer requests are generated by assertion of the transfer
Dual-address mode is the only address mode available for the DMAC in the TMP1942.
In dual-address mode, data transfers are performed between two memory devices or between
TMP1942CY/CZ-151
TMP1942CY/CZ