tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 198

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Note: Programming the TB0FF0C1[1:0] field should only be attempted when the timer is not running.
Note2: If the timer is stopped when only the eight low-order bits have been read, capture
Note3: When the TB0IN0 pin is selected as a capture trigger input, it can not function as a timer
Note1: Reading the eight low-order bits of the capture register disables capture operation.
(4) Capture registers (TB0CP0H/L and TB0CP1H/L)
(5) Capture controller
(6) Comparators (CP0 and CP1)
(7) Timer flip-flop (TB0FF0)
Data may be read out from a capture register in a single operation using a 2-byte data transfer
instruction, or in two operations (the eight low-order bits first and then the eight high-order bits)
using a 1-byte data transfer instruction.
capture registers (TB0CP0 and TB0CP1). The capture register latch timing is set using
TB0MOD<TB0CMPM1:TB0CMPM0>.
Each time TB0MOD<TB0CP0> is set to 0, the UC0 value at that point is latched into TB0CP0.
Before this function can be used, the prescaler must be placed in the Run state by setting
TB0RUN<TB0PRUN> to 1.
software capture.
timer registers TB0RG0 and TB0RG1 to detect a match. If the value in either TB0RG0 or TB0RG1
matches the value in UC0, the corresponding comparator generates an INTTB0 interrupt.
comparator or by a latch signal to the capture registers. Inversion can be enabled or disabled by
setting TB0FFCR<TB0C1T1,TB0C0T1,TB0E1T1,TB0E0T1> accordingly.
inverts the value of the flip-flop; writing 01 to TB0FFCR<TB0FF0C1,TB0FF0C0> sets the flip-flop
to 1; writing 10 to TB0FFCR<TB0FF0C1,TB0FF0C0> clears the flip-flop to 0.
timer output is needed, this pin must be set for that purpose by using the port A registers PACR and
PAFC.
operation is not enabled even after the timer is restarted. Do not stop the timer until both
the eight low-order and eight high-order bits are read.
clock.
TB0CP0H/L and TB0CP1H/L are 16-bit registers used to latch the value of the up-counter UC0.
This circuit controls the timing at which the value in the up-counter UC0 is latched into the
In addition, the value of the up-counter UC0 can be latched into the capture registers by software.
In 2-phase pulse counter mode (only for TMRB2 and TMRB3), the counter value is latched by
Subsequently reading the eight high-order bits of the capture register enables capture
operation.
The two 16-bit comparators compare the value of the up-counter UC0 with the values set in the
The timer flip-flop TB0FF0 is designed to be inverted by a match detection signal from the
When reset, the TB0FF0 value is undefined. Writing 00 to TB0FFCR<TB0FF0C1:TB0FF0C0>
The TB0FF0 value can be forwarded to the timer output pin, TB0OUT (shared with PA2). When
TMP1942CY/CZ-197
TX1942CY/CZ