tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 17

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

3.2
Note 1: The internal ROM is mapped into the memory space from 0x1FC0_0000 to 0x1FC3_FFFF (for a 256-KB ROM) or
Note 2: The memory space from 0xFFFF_4000 to 0xFFFF_BFFF is a reserved RAM area. Any area other than those shown above,
Note 3: The internal memory data is stored in contiguous physical address locations starting at 0x1FC0_0000.
Note 4: The TX1942 supports access to only 16 Mbytes of physical space as external address space. A 16-Mbyte physical address
Note 5: Do not place an instruction in the last four words of the physical area.
0xFFFF_FFFF
0xFF00_0000
0xC000_0000
0xBFC0_0000
0xA000_0000
0x8000_0000
0x0007_FFFF
0x0000_0000
Memory Map
0x1FC0_0000 to 0x1FC5_FFFF (for a 384-KB ROM). The internal RAM is mapped into the memory space from
0xFFFF_8000 to 0xFFFF_BFFF (for a 16-KB RAM).
where physical memory is located, should not be accessed.
If exception vector addresses are placed in internal ROM, the system control coprocessor (CP0) Status register's BEV bit
must be set to 1 (the default). (This is because exception vector addresses are dispersed if BEV = 0.) If memory is added
externally, the BEV bit can be set to 0.
However, since a virtual address space of 0x0000_0000 ±32 KB is easier to access for reasons of code efficiency, this area
is reflected in the contiguous physical address space from 0x4000_0000 upwards (as indicated by the shaded area) which
corresponds to a virtual address space starting at 0x0000_0000 and which is equal in size to the internal memory. Hence,
accessing this area is equivalent to accessing the internal memory.
Example: Using 32-bit ISA
space can be placed in any chip-select area within the CPU's 3.5 Gbytes of physical address space.
However, when access to the internal memory, internal I/O space or a reserved area is performed, the external address
space cannot be accessed simultaneously, since the other types of access have priority.
Figure 3.2.1 shows a memory map of the TMP1942.
• Access to the 0x0000_0000 ±32 KB area
• Access to areas other than 0x0000_0000 ±32 KB
• The relevant area of the internal ROM is 0x1FC3_FFF0 to 0x1FC3_FFFF (for a 256-KB ROM) or 0x1FC5_FFF0 to
• If ROM is added externally, this restriction applies to the last four words of the installed memory
0x1FC5_FFFF (for a 384-KB ROM).
(system-dependent).
ADDIU
SW
LUI
ADDIU
SW
16 Mbytes reserved
16 Mbytes reserved
Virtual address
(uncacheable)
(cacheable)
(cacheable)
(cacheable)
Kseg2
Kseg1
Kseg0
Kuseg
r2, r0, 7
r2, Io (_t) (r0) ; 0x0000_xxxx ← (r2)
Can be accessed using a single instruction.
r3, hi (_f)
r2, r0, 8
r2, Io (_f) (r3) ; Memory is accessed after lower address has been set.
↑
; r 2 ← (0x0000_0007)
; ← Upper address is set to r3.
; r2 ← (0x0000_0008)
Figure 3.2.1 Memory Map
TMP1942CY/CZ-16
Cannot be accessed
16 Mbytes reserved
16 Mbytes reserved
Internal ROM area
Physical address
Internal ROM
512 Mbytes
(1 Gbyte)
(2Gbyte)
reflected
Kseg2
Kuseg
0x4003_FFFF
0x4000_0000
0x1FC3_FFFF
0x1FC0_0000
TMP1942CY/CZ
Exception vector area
User program area
Maskable interrupt
Internal RAM (16KB)
debugging (2 MB)
Reserved for
Internal I/O
(Reserved)
(Reserved)
(Reserved)
area
0xFFFF_E000
0xFFFF_AFFF
0xFFFF_7000
0xFF3F_FFFF
0xFF20_0000
0x1FC3_FFFF
0x1FC0_0400
0x1FC0_0000
0xFF00_0000