tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 123

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Figure 3.6.8 Read Operation Timing Diagram (with ALE Asserted for 0.5 and 1.5 Clock Cycles)
(3) ALE assertion time
an ALE assertion time of 1.5 clock cycles.
Note: “Please set the number of wait as “+1” when you use = long and BUSRQ the ALE width.”
A [23 : 16]
AD [15 : 0]
ALE
RD
Figure 3.6.8 shows read operation timing with an ALE assertion time of 0.5 clock cycles and that with
ALE (ALESEL = 0)
AD [15 : 0]
(ALESEL = 1)
AD [15 : 0]
assertion time is provided in the system clock control register. The default assertion time is 1.5
clock cycles. The assertion time cannot be set individually for blocks in the external area; it applies
universally to the entire external address space.
The ALE assertion time can be selected as either 0.5 or 1.5 clock cycles. The bit for setting this
ADR
ALE 0.5 clock cycle
Upper address
Figure 3.6.7 ALE Assertion Time
tsys
DATA
TMP1942-122
ADR
tsys
0.5 clock cycle
ALE 1.5 clock cycles
Upper address
DATA
TMP1942CY/CZ
1.5 clock cycles