tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 119

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Note 1: Even for cases (3) and (4), addresses are output because the data bus pins are shared with the address
Note 2: Ports 0 to 2 are set for input after a reset, and do not function as address or data bus pins.
Note 3: Any one of (1) to (4) can be selected by setting the P1CR, P1FC, P2CR and P2FC registers as desired.
Number of address
bus lines
Number of data
bus lines
Number of multiplexed
address/data bus lines
Port
function
Timing diagram
3.6.1
bus.
Port 0
Port 1
Port 2
Address and data pins
(1) Setting address and data pins
(2) Address hold when an internal area is accessed
(A16-A23/A0-A7) pins can be used as the address bus and the data bus. One of the following four
bus configurations can be selected by setting up the port registers.
by the external area device; thus the address does not change. In addition, the address/data bus is
placed in high-impedance state.
For external memory connections, port 0 (AD0-AD7), port 1 (AD8-AD15/A8-A15) and port 2
When an internal area is accessed, the address bus retains the previous address which was output
A23~8
AD7~0
ALE
RD
max.24 (~16 MB)
AD0 ~ AD7
A16 ~ A23
A7~0
A8 ~ A15
(1)
A23~8
8
8
D7~0
TMP1942-118
A23~16
AD15~0
ALE
RD
max.24 (~16 MB)
AD8 ~ AD15
AD0 ~ AD7
A16 ~ A23
A15~0 D15~0
(2)
16
16
A23~16
A15~0
AD7~0
ALE
RD
max.16 (~64 KB)
AD0 ~ AD7
A8 ~ A15
A0 ~ A7
A7~0 D7~0
TMP1942CY/CZ
(3)
(Note1)
8
0
A15~0
A7~0
AD15~0
ALE
RD
max.8 (~256 B)
AD8 ~ AD15
AD0 ~ AD7
A0 ~ A7
A15~0
(4)
16
(Note1)
0
A7~0
D15~0