tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 36
tmp19a43fzxbg
Manufacturer Part Number
tmp19a43fzxbg
Description
32bit Tx System Risc
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMP19A43FZXBG.pdf
(406 pages)
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Input: The input gate is active; the input voltage must be held at either the high or low level to keep the input
Output: Pin direction is output.
PU*: Programmable pull-up. Because the input gate is always disabled, no overlap current flows while in
PE0~PE5
PE6~PE7
PF0,PF2~PF5
PF1
PF6
ALE
BW0, BW1
X1
X2
NMI
RESET
Pins configured for input mode and input-only pins are disabled. Pins configured for output mode and
output-only pins assume the high-Impedance state.
pin from floating.
high-impedance state.
Pins
Input mode
Output mode
Input mode
Output mode
Input mode(INT1,INT2)
Input mode
Output mode
Input mode
Output mode
Input mode(KEYD)
Input mode
Output mode
Input mode(INT0)
Input pin
Output pin
Input pin
Input pin
Input pin
Output pin
Input/Output
TMP1942CY/CZ-35
<DRVE> = 0
Output High
Output Low
Input
Input
Input
Input
Input
Input
-
-
-
-
-
-
-
-
-
-
-
TMP1942CY/CZ
<DRVE> = 1
Output High
Output Low
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
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