tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 144

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Rst
31
15
W
0
Note1: When the snoop request is disabled (CCRn.SReq=0), a software reset of the DMAC must be performed in
Note 2: If the software reset command is written to the DCR register immediately after the completion of the last
Note 3: Don’t issue a software reset command to the DCR register via a DMA transfer.
30
3.8.3.1
Bit
31
the following sequence:
Execute steps 3 and 4 consecutively.
transfer cycle of a DMA transaction, the DMA-done interrupt will not be cleared. In this case, the software
reset only initializes channel registers, etc.
1. Disable interrupts.
2. Execute NOP four times.
3. Perform a software reset.
4. Perform a software reset again.
5. Re-enable interrupts.
Mnemonic
DMA control register (DCR)
Rst
Reset
Figure 3.8.3 DMA Control Register (DCR)
Field Name
TMP1942CY/CZ-143
Reset (initial value: —)
Resets the DMAC by software. When the Rst bit is set to 1, all
of the DMAC’s internal registers are reset to their initial values.
Also, all transfer requests are canceled and the four DMA
channels are turned off.
0: Don’t care
1: Initialize the DMAC.
Description
TMP1942CY/CZ
16
0
: Type
: Initial value
: Type
: Initial value