tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 142

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

3.8.2.2
3.8.2.3
Note: When the snoop function is not used, the TX19 processor core does not release the data bus to the
Internal blocks of the DMAC
Snoop function
processor core’s data bus to the DMAC.
At the same time the TX19 processor core stops operating and remains idle until control of the data
bus is returned to it by the DMAC. Since the DMAC can access the processor’s internal RAM or
internal ROM while the snoop function is active, the RAM or ROM can be specified as the source or
destination of a transfer.
snoop function. If the DMAC chooses to use the snoop function, it can then access the processor’s
internal RAM and internal ROM. The CPU in the TX19 processor core will then be stalled until the
DMAC cancels the bus request.
RAM or internal ROM. However, since in this case too the G-Bus is released to the DMAC, if the
TX19 processor core attempts to access memory or I/O via the G-Bus and the DMAC does not
respond to the request for release of bus control, the TX19 processor core will not be able to execute
bus operation, and as a result the pipeline will stall.
DMAC. Therefore, if the processor’s internal RAM or internal ROM is specified as the source or
destination of a DMA transfer, no acknowledge signal will be returned for the DMAC’s transfer
cycle, resulting in the bus being locked.
Figure 3.8.2 shows the internal blocks of the DMAC.
The TX19 processor core has a snoop function. This function is used to release the TX19
When the snoop function is activated, the TX19 processor core releases its data bus to the DMAC.
The TMP1942’s internal DMAC can select whether or not to use the TX19 processor core’s
If the DMAC chooses not to use the snoop function, it cannot access the processor’s internal
Channel 3
Channel 2
Channel 1
Figure 3.8.2 Internal Blocks of the DMAC
Channel 0
31
Source address register (SAR0)
Destination address register (DAR0)
Byte count register (BCR0)
Channel control register (CCR0)
Channel status register (CSR0)
DMA transfer control register (DTCR0)
DMA control register(DCR)
Data holding register(DHR)
31
チャネル コントロ-ル レジスタ
デスティネ-ション アドレス レジスタ
Source アドレス Regisuter
TMP1942CY/CZ-141
チャネル Status レジスタ
Byte Count レジスタ
0
0
TMP1942CY/CZ