tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 155

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

3.8.4.2
Transfer requests
the DMAC. There are two types of DMAC transfer requests: internal transfer requests and external
transfer requests. The transfer request type can be set individually for each channel.
activated, the DMAC will gain control of the bus and perform data transfer.
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For data to be transferred by the DMAC, a transfer request must be generated and transmitted to
For either type of transfer request, when a transfer request occurs after channel operation has been
Internal transfer requests
1 while the ExR bit in the same register = 0. This transfer request is referred to as an internal
transfer request.
channel operation has been completed, data transfers will be performed successively unless
transition to a higher priority channel occurs or until bus control is transferred to a higher
priority bus master.
External transfer requests
by the assertion of the INTDREQn signal for a channel after the channel has been placed in
ready state by setting the Str bit of the CCRn register to 1 while the ExR bit in the CCRn
register = 0. This transfer request is referred to as an external transfer request. External transfer
requests can be used for transfers between two memory devices and between memory and an
I/O device.
edge or level is specified using the PosE bit in the CCRn register. However, because the
INTDREQn signal in the TMP1942 is low-active, always make sure that the signal is set to be
detected at Low level.
in the CCRn register. This can be specified as 32 bits, 16 bits or 8 bits.
The DACKn signal is asserted only when the number of bytes to be transferred during an I/O
device bus cycle or a memory-to-memory transfer (as specified by the value of the BCRn
register) falls to 0. Consequently, for data transfer between memory and an I/O device
INTDREQn is cancelled every transfer request with the result that only one transfer is
performed for the amount of data specified by TrSiz. On the other hand, in memory-to-memory
transfers, INTDREQn is not cancelled until the number of bytes to be transferred (as specified
by the value of the BCRn register) falls to 0; hence several data transfers can be performed
successively by a single transfer request.
but the interrupt is cleared by the interrupt controller or by another device before the DMAC
starts the DMA transfer, one DMA transfer may be performed after the interrupt has been
cleared.
A transfer request can be generated immediately by setting the Str bit in the CCRn register to
In the case of an internal transfer request, because the transfer request remains active until
Internal transfer requests can only be used for transfers between memory and memory.
A transfer request is generated when the interrupt controller is notified of a transfer request
Assertion of the INTDREQn signal is recognized by detecting an edge or a level. The active
The amount of data to be transferred for one transfer request is specified using the TrSiz field
Transfer requests from the interrupt controller are cleared by assertion of the DACKn signal.
Note that if an interrupt of the type specified for INTDREQn is acknowledged by the DMAC,
TMP1942CY/CZ-154
TMP1942CY/CZ