tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 228

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Note1: X = Don’t care; “–” = No change
Note2: Please do not stop a timer in PPG mode at the time of duty change (please use a double buffer).
(1) Change a timer output terminal to a PORT function.
(2) Timer stop (<TBnRUN>="0")
(3) Forbid a reversal output at the time of coincidence with a Up Counter and a Timer Register
(4) Start a timer (<TBnRUN>="1").
(5) Suspend a timer (<TBnRUN>="0").
(6) A setup of the contents of change.
(7) Change an output terminal from a PORT function to a timer output.
(8) Start a timer (<TBnRUN>="1").
(TBnFFCR<TBnE1T1:TBnE0T1>=00).
TB0RUN
TB0RG0
TB0RG1
TB0RUN
TB0FFCR
TB0MOD
P7CR
P7FC
TB0RUN
TB0RG0-WR
In order to change a timer-related setup, please perform the following setup, when you resume
after a stop (<TBnRUN>="0") (<TBnRUN>="1").
TB0IN0
φT16
Figure 3.10.
To use the timer in 16-bit PPG output mode, set each register as shown below.
φT1
φT4
← 0
← *
← *
← 1
← X
← 0
← −
← −
← 1
TB0RUN<TB0RDE>
7
Figure 3.10.32 16-Bit PPG Output Mode Block Diagram
Selector
6
0
*
*
0
X
0
1
1
0
Selector
32 shows a block diagram of 16-bit PPG output mode.
(** = 01, 10, 11)
5
X
*
*
X
0
1
−
−
X
4
X
*
*
X
0
0
−
−
X
3
−
*
*
−
1
0
−
−
−
16-bit comparator
Register buffer 0
2
0
*
*
0
1
1
−
−
1
TMP1942CY/CZ-227
TB0RG0
1
X
*
*
X
1
*
−
−
X
0
0
*
*
0
0
*
−
−
1
16-bit up-counter
Internal bus
Disable TB0RG0 double-buffer and stop TMRB0.
Set duty cycle (16 bits).
Set PPG cycle (16 bits).
Enable TB0RG0 double-buffer.
(Duty cycle and PPG cycle are changed by INTTB01 interrupt.)
Set TB0FF0 so that its value will be inverted on detecting a match
with TB0RG0 or TB0RG1. Also initialize TB0FF0 to 0.
Select prescaler output clock as input clock and disable capture
function.
Set PA2 pin to TB0OUT.
Start TMRB0.
Match
UC0
TB0RUN<TB0RUN>
16-bit comparator
TB0RG1
Clear
TB0OUT (PPB output)
TX1942CY/CZ
(TB0FF0)
F/F