tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 29

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

3.3.6
it has been activated, as does the oscillator.
SYSCR3<LUPTM> so that it satisfies the following relationship:
SYSCR3<LUPTM> remains 1 until the PLL is locked in phase and cleared to 0 upon the completion of
lock-up.
execution speed, such as real-time processing, is to be performed, the software must check the lock-up
flag after operation has started (i.e., after warm-up has been completed) to ensure that the clock has
settled, before it starts processing.
initialization, can be executed before the lock-up flag has been cleared.
Precautions to be observed when switching clock gear:
is not switched immediately after the write: a execution time equal to several clock cycles is required.
Therefore, one or more instructions following the clock gear switchover instruction may be executed
using the old clock gear value. If these instructions need to be executed using the new clock gear value,
insert a dummy instruction (which executes a write cycle only) after the clock gear switchover
instruction.
the following relationship:
Standby control unit
one of the standby modes - IDLE, SLEEP or STOP - as determined by the contents of
SYSCR2<STBY1:STBY0>. If the Config register's Doze bit is set, the device enters IDLE mode
regardless of the setting of SYSCR2<STBY1:STBY0>.
1) IDLE: In this mode, only the CPU stops.
Since the PLL is configured as an analog circuit, it requires a certain settling time (a lock-up time) after
The same timer is used for both warm-up and lock-up. The lock-up time must be set using
By default, the lock-up time is 2
The lock-up timer is initiated as the high-speed oscillator starts warm-up, and the lock-up flag
If, for example, the PLL gets out of lock in a standby mode and control which depends on the software's
On the other hand, various hardware settings and static processing, such as register and memory
Note: The LUPFG bit is undefined when the PLLOFF pin is Low (the PLL is not used).
Clock gear switchover is performed by writing a value to SYSCR1<GEAR1:GEAR0>. The clock gear
When using a clock gear, make sure that the prescaler output φTn in each peripheral I/O block satisfies
For this purpose set the clock-related registers so that φTn is slower than fsys/2.
If the Halt bit in the TX19 processor core's Config register is set in NORMAL mode, the device enters
Features of the IDLE, SLEEP and STOP modes are described below.
Lock-up time ≥ warm-up time
φTn < fsys/2
In the register corresponding to each module there is an IDLE mode run/stop setup bit for
internal I/O. This allows each module to be set independently to run or stop while the device is
in IDLE mode. Table 3.3.3 lists the IDLE setup registers available for each internal I/O
module.
TMP1942CY/CZ-28
16
/input frequency.
TMP1942CY/CZ