tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 146

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

8 : 7
5 : 4
3 : 2
1 : 0
Bit
12
11
10
9
6
Mnemonic
RelEn
SReq
TrSiz
SAC
DAC
DPS
DIO
Lev
SIO
Level Mode
Snoop Request
Bus Control Release
Request Enable
Source I/O
Source Address Count
Destination I/O
Destination Address
Count
Transfer Size
Device Port Size
Figure 3.8.4 Channel Control Registers (CCRn) (2/2)
Field Name
TMP1942CY/CZ-145
Level Mode (initial value: 0)
Specifies the method for requesting external transfer. This
specification is effective only when the transfer request is an external
transfer request (i.e., when the ExR bit = 1). In the case of internal
transfer requests (i.e., when the ExR bit = 0), the value of Lev is
ignored. Be sure to set the Lev bit to 1.
Snoop Request (initial value: 0)
Specifies whether or not the snoop function is to be used as the bus
control request mode. When the function is selected for use, the
TX19 processor core’s snoop function is activated with the result that
the DMAC can use the processor core’s data bus. When the function
is not selected for use, the TX19 processor core’s snoop function
remains inactive.
1: The snoop function is used (i.e., the device is in SREQ mode).
0: The snoop function is not used (i.e., the device is in GREQ mode).
Release Request Enable (initial value: 0)
Specifies whether the DMAC will respond to requests for release of
bus control issued from the TX19 processor core.
This function is only effective in GREQ mode. In SREQ mode, this
function would have no effect since the TX19 processor core cannot
generate a request for release of bus control.
1: After the DMAC has taken over bus control, it will respond to
0: The DMAC will not respond to requests for release of bus control.
Source Type: I/O (initial value: 0)
Specifies the source device from which to perform transfer.
1: I/O device
0: Memory
Source Address Count (initial value: 00)
Specifies the way in which the source address changes.
1x: The address is fixed.
01: The address is decremented.
00: The address is incremented.
Destination Type: I/O (initial value: 0)
Specifies the destination device to which to perform transfer.
1: I/O device
0: Memory
Destination Address Count (initial value: 00)
Specifies the way in which the destination address changes.
1x: The address is fixed.
01: The address is decremented.
00: The address is incremented.
Transfer Size (initial value: 00)
Indicates the amount of data to be transferred in response to one
transfer request.
11: 8 bits (1 byte)
10: 16 bits (2 bytes)
0x: 32 bits (4 bytes)
Device Port Size (initial value: 00)
Specifies the bus width for the I/O device which has been specified
as the source or destination device.
11: 8 bits (1 byte)
10: 16 bits (2 bytes)
0x: 32 bits (4 bytes)
requests for release of bus control. When the TX19 processor core
issues a request for release of bus control, the DMAC will return
control of the bus to the TX19 processor core when a break in bus
operation occurs.
Description
TMP1942CY/CZ