PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 108

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

www.national.com
5.7.23 The VERSION Command
The VERSION command returns the version number of the
current Floppy Disk Controller (FDC).
Command Phase
Execution Phase
None.
Result Phase
The result phase byte returns a value of 90h for an FDC that
is compatible with the 82077.
Other controllers, i.e., the DP8473 and other NEC765 com-
patible controllers, return a value of 80h (invalid command).
5.7.24 The WRITE DATA Command
The WRITE DATA command receives data from the host
and writes logical sectors containing a normal data Address
Mark (AM) to the selected drive.
This command is like the READ DATA command, except
that the data is transferred from the microprocessor to the
controller instead of the other way around.
Command Phase
See the READ DATA command starting on page 96 for a
description of these bytes.
The controller waits the Delay Before Processing time be-
fore starting execution.
If implied seeks are enabled, i.e., IPS in the second com-
mand phase byte is 1, the operations performed by SEEK
and SENSE INTERRUPT commands are performed (with-
out these commands being issued).
IPS
MT
7
0
7
1
7
MFM
X
6
0
6
0
6
End of Track (EOT) Sector Number
Bytes Between Sectors - Gap 3
X
Data Length (Obsolete)
5
0
5
0
5
0
Bytes-Per-Sector Code
Sector Number
Track Number
Head Number
X
4
1
4
1
4
0
X
3
0
3
0
3
0
HD
2
0
2
0
2
1
DS1
1
0
1
0
1
0
DS0
0
0
0
0
0
1
108
Execution Phase
Data is transferred from the system to the controller via
DMA or non-DMA modes and written to the disk.See “Exe-
cution Phase” starting on page 78 for a description of these
data transfer modes.
The controller starts the data separator and waits for it to
find the address field of the next sector. The controller com-
pares the address ID (track number, head number, sector
number, bytes-per-sector code) with the ID specified in the
command phase.
If there is no match, the controller waits to find the next sec-
tor address field. This process continues until the desired
sector is found. If an error condition occurs, the Interrupt
Control (IC) bits (bits 7,6) in ST0 are set to abnormal termi-
nation, and the controller enters the result phase. See “Bits
7,6 - Interrupt Code (IC)” on page 81.
Possible errors are:
If the correct address field is found, the controller waits for
all (conventional drive mode) or part (perpendicular drive
mode) of gap 2 to pass. See Figure 5-20 on page 91. The
controller then writes the preamble field, Address Marks
(AM) and data bytes to the data field. The microprocessor
transfers the data bytes to the controller.
After writing the sector, the controller reads the next logical
sector, unless one or more of the following termination con-
ditions occurs:
•
•
•
•
•
•
The microprocessor aborted the command by writing to
the FIFO.
If there is no disk in the drive, the controller gets stuck.
The microprocessor must then write a byte to the FIFO
to advance the controller to the result phase.
Two pulses of the INDEX signal were detected since the
search began, and no valid ID was found.
If the track address differs, either the Wrong Track bit
(bit 4) or the Bad Track bit (bit 1) (if the track address is
FFh is set in result phase Status register 2 (ST2). See
Section 5.5.3 on page 82.
If the head number, sector number or bytes-per-sector
code did not match, the Missing Data bit (bit 2) is set in
result phase Status register 1 (ST1).
If the Address Mark (AM) is not found, the Missing Ad-
dress Mark bit (bit 0) is set in ST1.
Section 5.5.2 on page 81 describes the bits of ST1.
A CRC error was detected in the address field. In this
case the CRC Error bit (bit 5) is set in ST1.
The controller detected an active the Write Protect (WP)
disk interface input signal, and set bit 1 of ST1 to 1.
The DMA controller asserted the Terminal Count (TC)
signal to indicate that the operation terminated. The In-
terrupt Code (IC) bits (bits 7,6) in ST0 are set to normal
termination (00). See page 81.
The last sector address (of side 1, if the Multi-Track en-
able bit (MT) was set to 1) was equal to the End of Track
sector number. The End of Track bit (bit 7) in ST1 is set.
The IC bits in ST0 are set to abnormal termination (01).
This is the expected condition during non-DMA trans-
fers.